forked from OSchip/llvm-project
224 lines
9.1 KiB
TableGen
224 lines
9.1 KiB
TableGen
//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// InstrSchedModel annotations for out-of-order CPUs.
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// Instructions with folded loads need to read the memory operand immediately,
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// but other register operands don't have to be read until the load is ready.
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// These operands are marked with ReadAfterLd.
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def ReadAfterLd : SchedRead;
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// Instructions with both a load and a store folded are modeled as a folded
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// load + WriteRMW.
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def WriteRMW : SchedWrite;
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// Most instructions can fold loads, so almost every SchedWrite comes in two
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// variants: With and without a folded load.
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// An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
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// with a folded load.
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class X86FoldableSchedWrite : SchedWrite {
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// The SchedWrite to use when a load is folded into the instruction.
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SchedWrite Folded;
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}
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// Multiclass that produces a linked pair of SchedWrites.
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multiclass X86SchedWritePair {
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// Register-Memory operation.
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def Ld : SchedWrite;
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// Register-Register operation.
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def NAME : X86FoldableSchedWrite {
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let Folded = !cast<SchedWrite>(NAME#"Ld");
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}
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}
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// Loads, stores, and moves, not folded with other operations.
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def WriteLoad : SchedWrite;
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def WriteStore : SchedWrite;
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def WriteMove : SchedWrite;
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// Arithmetic.
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defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
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def WriteALURMW : WriteSequence<[WriteALULd, WriteStore]>;
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defm WriteIMul : X86SchedWritePair; // Integer multiplication.
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def WriteIMulH : SchedWrite; // Integer multiplication, high part.
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defm WriteIDiv : X86SchedWritePair; // Integer division.
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def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
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defm WriteBitScan : X86SchedWritePair; // Bit scan forward/reverse.
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defm WritePOPCNT : X86SchedWritePair; // Bit population count.
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defm WriteLZCNT : X86SchedWritePair; // Leading zero count.
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defm WriteTZCNT : X86SchedWritePair; // Trailing zero count.
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defm WriteCMOV : X86SchedWritePair; // Conditional move.
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def WriteSETCC : SchedWrite; // Set register based on condition code.
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def WriteSETCCStore : SchedWrite;
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// Integer shifts and rotates.
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defm WriteShift : X86SchedWritePair;
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// BMI1 BEXTR, BMI2 BZHI
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defm WriteBEXTR : X86SchedWritePair;
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defm WriteBZHI : X86SchedWritePair;
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// Idioms that clear a register, like xorps %xmm0, %xmm0.
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// These can often bypass execution ports completely.
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def WriteZero : SchedWrite;
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// Branches don't produce values, so they have no latency, but they still
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// consume resources. Indirect branches can fold loads.
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defm WriteJump : X86SchedWritePair;
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// Floating point. This covers both scalar and vector operations.
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def WriteFLoad : SchedWrite;
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def WriteFStore : SchedWrite;
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def WriteFMove : SchedWrite;
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defm WriteFAdd : X86SchedWritePair; // Floating point add/sub.
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defm WriteFCmp : X86SchedWritePair; // Floating point compare.
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defm WriteFCom : X86SchedWritePair; // Floating point compare to flags.
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defm WriteFMul : X86SchedWritePair; // Floating point multiplication.
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defm WriteFDiv : X86SchedWritePair; // Floating point division.
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defm WriteFSqrt : X86SchedWritePair; // Floating point square root.
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defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal estimate.
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defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate.
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defm WriteFMA : X86SchedWritePair; // Fused Multiply Add.
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defm WriteFMAS : X86SchedWritePair; // Fused Multiply Add (Scalar).
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defm WriteFMAY : X86SchedWritePair; // Fused Multiply Add (YMM/ZMM).
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defm WriteFSign : X86SchedWritePair; // Floating point fabs/fchs.
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defm WriteFLogic : X86SchedWritePair; // Floating point and/or/xor logicals.
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defm WriteFLogicY : X86SchedWritePair; // Floating point and/or/xor logicals (YMM/ZMM).
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defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles.
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defm WriteFVarShuffle : X86SchedWritePair; // Floating point vector variable shuffles.
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defm WriteFVarShuffleY : X86SchedWritePair; // Floating point vector variable shuffles (YMM/ZMM).
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defm WriteFBlend : X86SchedWritePair; // Floating point vector blends.
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defm WriteFBlendY : X86SchedWritePair; // Floating point vector blends (YMM/ZMM).
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defm WriteFVarBlend : X86SchedWritePair; // Fp vector variable blends.
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defm WriteFVarBlendY : X86SchedWritePair; // Fp vector variable blends (YMM/ZMM).
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// FMA Scheduling helper class.
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class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
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// Horizontal Add/Sub (float and integer)
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defm WriteFHAdd : X86SchedWritePair;
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defm WriteFHAddY : X86SchedWritePair; // YMM/ZMM.
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defm WritePHAdd : X86SchedWritePair;
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// Vector integer operations.
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def WriteVecLoad : SchedWrite;
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def WriteVecStore : SchedWrite;
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def WriteVecMove : SchedWrite;
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defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals.
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defm WriteVecLogic : X86SchedWritePair; // Vector integer and/or/xor logicals.
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defm WriteVecShift : X86SchedWritePair; // Vector integer shifts.
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defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply.
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defm WritePMULLD : X86SchedWritePair; // PMULLD
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defm WriteShuffle : X86SchedWritePair; // Vector shuffles.
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defm WriteVarShuffle : X86SchedWritePair; // Vector variable shuffles.
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defm WriteBlend : X86SchedWritePair; // Vector blends.
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defm WriteVarBlend : X86SchedWritePair; // Vector variable blends.
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defm WritePSADBW : X86SchedWritePair; // Vector PSADBW.
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defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
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defm WritePHMINPOS : X86SchedWritePair; // Vector PHMINPOS.
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// Vector insert/extract operations.
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defm WriteVecInsert : X86SchedWritePair; // Insert gpr to vector element.
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def WriteVecExtract : SchedWrite; // Extract vector element to gpr.
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def WriteVecExtractSt : SchedWrite; // Extract vector element and store.
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// MOVMSK operations.
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def WriteFMOVMSK : SchedWrite;
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def WriteVecMOVMSK : SchedWrite;
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def WriteMMXMOVMSK : SchedWrite;
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// Conversion between integer and float.
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defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer.
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defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float.
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defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion.
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def WriteCvtF2FSt : SchedWrite; // // Float -> Float + store size conversion.
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// CRC32 instruction.
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defm WriteCRC32 : X86SchedWritePair;
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// Strings instructions.
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// Packed Compare Implicit Length Strings, Return Mask
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defm WritePCmpIStrM : X86SchedWritePair;
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// Packed Compare Explicit Length Strings, Return Mask
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defm WritePCmpEStrM : X86SchedWritePair;
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// Packed Compare Implicit Length Strings, Return Index
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defm WritePCmpIStrI : X86SchedWritePair;
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// Packed Compare Explicit Length Strings, Return Index
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defm WritePCmpEStrI : X86SchedWritePair;
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// AES instructions.
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defm WriteAESDecEnc : X86SchedWritePair; // Decryption, encryption.
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defm WriteAESIMC : X86SchedWritePair; // InvMixColumn.
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defm WriteAESKeyGen : X86SchedWritePair; // Key Generation.
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// Carry-less multiplication instructions.
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defm WriteCLMul : X86SchedWritePair;
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// Load/store MXCSR
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def WriteLDMXCSR : SchedWrite;
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def WriteSTMXCSR : SchedWrite;
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// Catch-all for expensive system instructions.
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def WriteSystem : SchedWrite;
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// AVX2.
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defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles.
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defm WriteFVarShuffle256 : X86SchedWritePair; // Fp 256-bit width variable shuffles.
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defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles.
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defm WriteVarShuffle256 : X86SchedWritePair; // 256-bit width vector variable shuffles.
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defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts.
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// Old microcoded instructions that nobody use.
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def WriteMicrocoded : SchedWrite;
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// Fence instructions.
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def WriteFence : SchedWrite;
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// Nop, not very useful expect it provides a model for nops!
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def WriteNop : SchedWrite;
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//===----------------------------------------------------------------------===//
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// Generic Processor Scheduler Models.
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// IssueWidth is analogous to the number of decode units. Core and its
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// descendents, including Nehalem and SandyBridge have 4 decoders.
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// Resources beyond the decoder operate on micro-ops and are bufferred
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// so adjacent micro-ops don't directly compete.
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//
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// MicroOpBufferSize > 1 indicates that RAW dependencies can be
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// decoded in the same cycle. The value 32 is a reasonably arbitrary
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// number of in-flight instructions.
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//
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// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
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// indicates high latency opcodes. Alternatively, InstrItinData
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// entries may be included here to define specific operand
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// latencies. Since these latencies are not used for pipeline hazards,
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// they do not need to be exact.
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//
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// The GenericX86Model contains no instruction schedules
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// and disables PostRAScheduler.
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class GenericX86Model : SchedMachineModel {
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let IssueWidth = 4;
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let MicroOpBufferSize = 32;
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let LoadLatency = 4;
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let HighLatency = 10;
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let PostRAScheduler = 0;
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let CompleteModel = 0;
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}
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def GenericModel : GenericX86Model;
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// Define a model with the PostRAScheduler enabled.
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def GenericPostRAModel : GenericX86Model {
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let PostRAScheduler = 1;
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}
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