llvm-project/llvm/test/CodeGen
LemonBoy 700eadca5f [SPARC] Fix type for i64 inline asm operands
Differential Revision: https://reviews.llvm.org/D101694
2022-06-04 18:32:16 -04:00
..
AArch64 [SVE] Refactor sve-bitcast.ll to include all combinations for legal types. 2022-06-03 12:09:19 +01:00
AMDGPU AMDGPU: allow reordering of functions in AMDGPUResourceUsageAnalysis 2022-06-03 15:55:54 -05:00
ARC
ARM [ARM] Make a narrow tMOVi8 where possible in SEH prologues 2022-06-03 22:33:55 +03:00
AVR [FileCheck] Catch missspelled directives. 2022-05-26 11:37:19 +01:00
BPF [Support] Make report_fatal_error respect its GenCrashDiag argument so it doesn't generate a backtrace 2022-05-30 19:19:23 +01:00
CSKY
DirectX [DirectX backend] When cleanup module flags only remove unused flags. 2022-05-19 14:50:11 -07:00
Generic [llvm][DWARF] Move test using X86 triple into X86 tests 2022-05-26 09:27:23 +00:00
Hexagon [Hexagon] Enable IAS in the Hexagon backend 2022-06-03 18:15:12 -04:00
Inputs
Lanai [Support] Make report_fatal_error respect its GenCrashDiag argument so it doesn't generate a backtrace 2022-05-30 19:19:23 +01:00
LoongArch
M68k [M68k] Instruction selection to choose neg x when mul x -1 (Fix issue 48588) 2022-06-03 13:20:30 +08:00
MIR [IR] Enable opaque pointers by default 2022-06-02 09:40:56 +02:00
MLRegalloc [mlgo] Fix test 2022-05-11 10:07:40 -07:00
MSP430
Mips [IR] Enable opaque pointers by default 2022-06-02 09:40:56 +02:00
NVPTX [NVPTX] Enable AtomicExpandPass for NVPTX 2022-05-20 17:25:28 -04:00
PowerPC [IR] Enable opaque pointers by default 2022-06-02 09:40:56 +02:00
RISCV [RISCV] Add more patterns for FNMADD 2022-06-04 12:31:45 +08:00
SPARC [SPARC] Fix type for i64 inline asm operands 2022-06-04 18:32:16 -04:00
SPIRV [SPIRV] Add simple tests to improve test coverage 2022-05-19 01:44:38 +03:00
SystemZ [IR] Enable opaque pointers by default 2022-06-02 09:40:56 +02:00
Thumb [ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4. 2022-06-02 00:49:11 +00:00
Thumb2 [ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4. 2022-06-02 00:49:11 +00:00
VE
WebAssembly [SSAUpdaterImpl] Do not generate phi node with all the same incoming values 2022-06-03 12:24:33 +07:00
WinCFGuard
WinEH
X86 Revert "[X86] combineConcatVectorOps - add support for concatenation VSELECT/BLENDV nodes" 2022-06-03 12:31:11 -07:00
XCore