forked from OSchip/llvm-project
196 lines
6.8 KiB
YAML
196 lines
6.8 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOVL --check-prefix=SSE2
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOVL --check-prefix=AVX1
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BWVL
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--- |
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define <16 x i8> @test_add_v16i8(<16 x i8> %arg1, <16 x i8> %arg2) {
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%ret = add <16 x i8> %arg1, %arg2
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ret <16 x i8> %ret
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}
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define <8 x i16> @test_add_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) {
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%ret = add <8 x i16> %arg1, %arg2
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ret <8 x i16> %ret
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}
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define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
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%ret = add <4 x i32> %arg1, %arg2
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ret <4 x i32> %ret
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}
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define <2 x i64> @test_add_v2i64(<2 x i64> %arg1, <2 x i64> %arg2) {
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%ret = add <2 x i64> %arg1, %arg2
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ret <2 x i64> %ret
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}
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...
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---
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name: test_add_v16i8
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# ALL-LABEL: name: test_add_v16i8
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alignment: 4
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legalized: true
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regBankSelected: true
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# NOVL: registers:
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# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
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# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
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#
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# AVX512BWVL: registers:
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# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
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# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# SSE2: %2:vr128 = PADDBrr %0, %1
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#
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# AVX1: %2:vr128 = VPADDBrr %0, %1
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#
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# AVX512VL: %2:vr128 = VPADDBrr %0, %1
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#
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# AVX512BWVL: %2:vr128x = VPADDBZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<16 x s8>) = COPY %xmm0
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%1(<16 x s8>) = COPY %xmm1
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%2(<16 x s8>) = G_ADD %0, %1
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%xmm0 = COPY %2(<16 x s8>)
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RET 0, implicit %xmm0
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...
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---
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name: test_add_v8i16
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# ALL-LABEL: name: test_add_v8i16
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alignment: 4
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legalized: true
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regBankSelected: true
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# NOVL: registers:
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# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
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# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
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#
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# AVX512BWVL: registers:
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# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
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# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# SSE2: %2:vr128 = PADDWrr %0, %1
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#
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# AVX1: %2:vr128 = VPADDWrr %0, %1
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#
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# AVX512VL: %2:vr128 = VPADDWrr %0, %1
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#
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# AVX512BWVL: %2:vr128x = VPADDWZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<8 x s16>) = COPY %xmm0
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%1(<8 x s16>) = COPY %xmm1
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%2(<8 x s16>) = G_ADD %0, %1
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%xmm0 = COPY %2(<8 x s16>)
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RET 0, implicit %xmm0
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...
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---
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name: test_add_v4i32
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# ALL-LABEL: name: test_add_v4i32
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alignment: 4
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legalized: true
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regBankSelected: true
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# NOVL: registers:
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# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
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# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
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#
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# AVX512BWVL: registers:
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# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
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# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# SSE2: %2:vr128 = PADDDrr %0, %1
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#
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# AVX1: %2:vr128 = VPADDDrr %0, %1
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#
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# AVX512VL: %2:vr128x = VPADDDZ128rr %0, %1
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#
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# AVX512BWVL: %2:vr128x = VPADDDZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<4 x s32>) = COPY %xmm0
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%1(<4 x s32>) = COPY %xmm1
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%2(<4 x s32>) = G_ADD %0, %1
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%xmm0 = COPY %2(<4 x s32>)
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RET 0, implicit %xmm0
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...
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---
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name: test_add_v2i64
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# ALL-LABEL: name: test_add_v2i64
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alignment: 4
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legalized: true
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regBankSelected: true
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# NOVL: registers:
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# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
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# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
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#
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# AVX512BWVL: registers:
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# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
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# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# SSE2: %2:vr128 = PADDQrr %0, %1
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#
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# AVX1: %2:vr128 = VPADDQrr %0, %1
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#
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# AVX512VL: %2:vr128x = VPADDQZ128rr %0, %1
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#
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# AVX512BWVL: %2:vr128x = VPADDQZ128rr %0, %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<2 x s64>) = COPY %xmm0
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%1(<2 x s64>) = COPY %xmm1
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%2(<2 x s64>) = G_ADD %0, %1
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%xmm0 = COPY %2(<2 x s64>)
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RET 0, implicit %xmm0
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...
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