llvm-project/mlir/test
Tobias Gysi 10643c9ad8 [mlir] make the bitwidth of device side index computations configurable (reland)
Summary:
The patch makes the index type lowering of the GPU to NVVM/ROCDL conversion configurable. It introduces a pass option that controls the bitwidth used when lowering index computations and uses the LowerToLLVMOptions structure to control the Standard to LLVM lowering.

This commit fixes a use-after-free bug introduced by the reverted commit d10b1a3. It implements the following changes:
- Added a getDefaultOptions method to the LowerToLLVMOptions struct that returns a reference to statically allocated default options.
- Use the getDefaultOptions method to provide default LowerToLLVMOptions (instead of an initializer list).
- Added comments to clarify the required lifetime of the LowerToLLVMOptions

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D82475
2020-06-29 12:22:39 +02:00
..
Analysis Change filecheck default to dump input on failure 2020-06-09 18:57:46 +00:00
Conversion [mlir] make the bitwidth of device side index computations configurable (reland) 2020-06-29 12:22:39 +02:00
Dialect [mlir] LLVM dialect: use addressof instead of constant to create function pointers 2020-06-29 12:21:33 +02:00
EDSC [mlir][EDSC] Add divis and diviu and vector.extractelement 2020-06-25 08:11:30 -07:00
Examples [lit] Improve naming of test result categories 2020-06-05 08:14:42 -07:00
IR [mlir] do not hardcode the name of the undefined function in the error message 2020-06-29 10:05:06 +02:00
Pass [mlir] Add a new context flag for disabling/enabling multi-threading 2020-05-02 12:32:25 -07:00
SDBM [MLIR] Reapply: Adjust libMLIR building to more closely follow libClang 2020-05-04 20:47:57 -07:00
Target [mlir] LLVM dialect: use addressof instead of constant to create function pointers 2020-06-29 12:21:33 +02:00
Transforms [mlir] fix off-by-one error in collapseParallelLoops 2020-06-26 15:39:46 +02:00
Unit Add build files and update README. 2019-03-30 11:23:22 -07:00
lib [MLIR] Remove TableGen redundant calls to native calls when creating new operations in DRR TableGen files 2020-06-22 08:12:04 -07:00
mlir-cpu-runner [mlir] support returning unranked memrefs 2020-06-26 15:37:37 +02:00
mlir-cuda-runner [MLIR][Standard] Make the `dim` operation index an operand. 2020-06-10 13:54:47 +00:00
mlir-linalg-ods-gen [mlir][Linalg] Add support to lower named ops to loops. 2020-04-30 13:45:17 -04:00
mlir-opt [mlir] Change dialect namespace loop->scf 2020-05-13 19:20:21 +02:00
mlir-rocm-runner [mlir][rocdl] Fixing breakage of dim operator from 904f91db 2020-06-11 17:35:22 +00:00
mlir-tblgen [mlir-tblgen] Use fully qualified names in generated code files 2020-06-26 15:05:33 +02:00
mlir-vulkan-runner [mlir][vulkan-runner] add support for memref of i8, i16 types in vulkan runner 2020-06-18 13:24:51 -07:00
APITest.h Mass update the MLIR license header to mention "Part of the LLVM project" 2020-01-26 03:58:30 +00:00
CMakeLists.txt [mlir][gpu] Introduce mlir-rocm-runner. 2020-06-05 09:46:39 -05:00
lit.cfg.py Fix `check-mlir` target when the host target isn't configured 2020-06-19 06:36:20 +00:00
lit.site.cfg.py.in [mlir][gpu] Introduce mlir-rocm-runner. 2020-06-05 09:46:39 -05:00