Luís Marques ec4f06a77d [RISCV] Don't crash on unsupported relocations ... Summary: Instead of crashing due to the `llvm_unreachable`, provide a proper error when invalid fixups/relocations are encountered. Reviewers: asb, lenary Reviewed By: asb Tags: #llvm Differential Revision: https://reviews.llvm.org/D71536		2019-12-19 17:21:30 +00:00
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AsmParser	[RISCV] Move DebugLoc Copy into CompressInstEmitter	2019-12-13 20:01:04 +00:00
Disassembler	[cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"	2019-11-21 10:48:08 -08:00
MCTargetDesc	[RISCV] Don't crash on unsupported relocations	2019-12-19 17:21:30 +00:00
TargetInfo	[cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"	2019-11-21 10:48:08 -08:00
Utils	[RISCV] Machine Operand Flag Serialization	2019-12-09 13:18:32 +00:00
CMakeLists.txt	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
LLVMBuild.txt	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCV.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCV.td	[RISCV] Improve assembler missing feature warnings	2019-12-10 16:44:48 +00:00
RISCVAsmPrinter.cpp	[RISCV] Support z and i operand modifiers	2019-07-08 05:00:26 +00:00
RISCVCallLowering.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVCallLowering.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVCallingConv.td	[RISCV] Rename FPRs and use Register arithmetic	2019-09-27 15:49:10 +00:00
RISCVExpandPseudoInsts.cpp	[RISCV] Use addi rather than add x0	2019-11-14 18:43:38 +00:00
RISCVFrameLowering.cpp	[RISCV] Handle variable sized objects with the stack need to be realigned	2019-11-16 12:39:53 +08:00
RISCVFrameLowering.h	[RISCV] Handle variable sized objects with the stack need to be realigned	2019-11-16 12:39:53 +08:00
RISCVISelDAGToDAG.cpp	Fix uninitialized variable warning. NFCI.	2019-11-13 14:40:21 +00:00
RISCVISelLowering.cpp	[IR] Split out target specific intrinsic enums into separate headers	2019-12-11 18:02:14 -08:00
RISCVISelLowering.h	[RISCV] Implement the TargetLowering::getRegisterByName hook	2019-11-04 11:23:54 +00:00
RISCVInstrFormats.td	[RISCV] Implement pseudo instructions for load/store from a symbol address.	2019-02-20 03:31:32 +00:00
RISCVInstrFormatsC.td	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCVInstrInfo.cpp	[RISCV] Enable the machine outliner for RISC-V	2019-12-19 16:41:53 +00:00
RISCVInstrInfo.h	[RISCV] Enable the machine outliner for RISC-V	2019-12-19 16:41:53 +00:00
RISCVInstrInfo.td	[RISCV][NFC] Trivial cleanup	2019-12-17 11:44:35 +00:00
RISCVInstrInfoA.td	Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"	2019-09-19 16:26:14 +00:00
RISCVInstrInfoC.td	[RISCV] Added missing ImmLeaf predicates	2019-10-04 23:42:07 +00:00
RISCVInstrInfoD.td	[RISCV] Handle fcopysign(f32, f64) and fcopysign(f64, f32)	2019-11-26 14:26:31 +00:00
RISCVInstrInfoF.td	[RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr)	2019-10-03 15:47:28 +00:00
RISCVInstrInfoM.td	[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M	2019-01-25 05:11:34 +00:00
RISCVInstructionSelector.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVMCInstLower.cpp	[RISCV] Add lowering of global TLS addresses	2019-06-19 08:40:59 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Delete a ctor that is commented out. NFC	2019-07-05 08:25:14 +00:00
RISCVMergeBaseOffset.cpp	[RISCV] Convert registers from unsigned to Register	2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterBankInfo.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterBanks.td	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp	[RISCV] Handle variable sized objects with the stack need to be realigned	2019-11-16 12:39:53 +08:00
RISCVRegisterInfo.h	[RISCV] Add support for -ffixed-xX flags	2019-10-22 21:25:01 +01:00
RISCVRegisterInfo.td	[RISCV] Rename FPRs and use Register arithmetic	2019-09-27 15:49:10 +00:00
RISCVSubtarget.cpp	[RISCV] Add support for -ffixed-xX flags	2019-10-22 21:25:01 +01:00
RISCVSubtarget.h	[RISCV] Add support for -ffixed-xX flags	2019-10-22 21:25:01 +01:00
RISCVSystemOperands.td	[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references	2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp	[RISCV] Enable the machine outliner for RISC-V	2019-12-19 16:41:53 +00:00
RISCVTargetMachine.h	[RISCV] Add subtargets initialized with target feature	2019-12-17 09:34:01 -08:00
RISCVTargetObjectFile.cpp	Revert "Honor -fuse-init-array when os is not specified on x86"	2019-12-17 07:36:59 -08:00
RISCVTargetObjectFile.h	[RISCV] Put data smaller than eight bytes to small data section	2019-04-11 04:59:13 +00:00
RISCVTargetTransformInfo.cpp	Rename TTI::getIntImmCost for instructions and intrinsics	2019-12-11 18:00:20 -08:00
RISCVTargetTransformInfo.h	Rename TTI::getIntImmCost for instructions and intrinsics	2019-12-11 18:00:20 -08:00