forked from OSchip/llvm-project
7bed381eae
`saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849 |
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| .. | ||
| crc | ||
| dsp | ||
| dspr2 | ||
| eva | ||
| ginv | ||
| micromips-dsp | ||
| micromips-dspr2 | ||
| micromips-dspr3 | ||
| micromips32r3 | ||
| micromips32r6 | ||
| mips1 | ||
| mips2 | ||
| mips3 | ||
| mips4 | ||
| mips32 | ||
| mips32r2 | ||
| mips32r3 | ||
| mips32r5 | ||
| mips32r6 | ||
| mips64 | ||
| mips64r2 | ||
| mips64r3 | ||
| mips64r5 | ||
| mips64r6 | ||
| msa | ||
| mt | ||
| octeon | ||
| octeonp | ||
| virt | ||
| lit.local.cfg | ||