forked from OSchip/llvm-project
147 lines
6.0 KiB
LLVM
147 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi -mcpu=krait | FileCheck %s
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define void @func1(i16* %a, i16* %b, i16* %c) {
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; CHECK-LABEL: func1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: add r3, r1, #16
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; CHECK-NEXT: vldr d18, [r2, #16]
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; CHECK-NEXT: vld1.16 {d16}, [r3:64]
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; CHECK-NEXT: vmovl.u16 q8, d16
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; CHECK-NEXT: vaddw.s16 q10, q8, d18
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; CHECK-NEXT: vmovn.i32 d19, q10
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; CHECK-NEXT: vldr d20, [r0, #16]
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; CHECK-NEXT: vstr d19, [r0, #16]
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; CHECK-NEXT: vldr d19, [r2, #16]
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; CHECK-NEXT: vmull.s16 q11, d18, d19
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; CHECK-NEXT: vmovl.s16 q9, d19
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; CHECK-NEXT: vmla.i32 q11, q8, q9
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; CHECK-NEXT: vmovn.i32 d16, q11
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; CHECK-NEXT: vstr d16, [r1, #16]
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; CHECK-NEXT: vldr d16, [r2, #16]
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; CHECK-NEXT: vmlal.s16 q11, d16, d20
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; CHECK-NEXT: vmovn.i32 d16, q11
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; CHECK-NEXT: vstr d16, [r0, #16]
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; CHECK-NEXT: bx lr
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entry:
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; The test case trying to vectorize the pseudo code below.
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; a[i] = b[i] + c[i];
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; b[i] = a[i] * c[i];
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; a[i] = b[i] + a[i] * c[i];
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; Checking that vector load a[i] for "a[i] = b[i] + a[i] * c[i]" is
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; scheduled before the first vector store to "a[i] = b[i] + c[i]".
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; Checking that there is no vector load a[i] scheduled between the vector
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; stores to a[i], otherwise the load of a[i] will be polluted by the first
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; vector store to a[i].
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; This test case check that the chain information is updated during
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; lowerMUL for the new created Load SDNode.
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%scevgep0 = getelementptr i16, i16* %a, i32 8
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%vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>*
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%vec0 = load <4 x i16>, <4 x i16>* %vector_ptr0, align 8
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%scevgep1 = getelementptr i16, i16* %b, i32 8
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%vector_ptr1 = bitcast i16* %scevgep1 to <4 x i16>*
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%vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
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%0 = zext <4 x i16> %vec1 to <4 x i32>
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%scevgep2 = getelementptr i16, i16* %c, i32 8
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%vector_ptr2 = bitcast i16* %scevgep2 to <4 x i16>*
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%vec2 = load <4 x i16>, <4 x i16>* %vector_ptr2, align 8
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%1 = sext <4 x i16> %vec2 to <4 x i32>
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%vec3 = add <4 x i32> %1, %0
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%2 = trunc <4 x i32> %vec3 to <4 x i16>
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%scevgep3 = getelementptr i16, i16* %a, i32 8
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%vector_ptr3 = bitcast i16* %scevgep3 to <4 x i16>*
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store <4 x i16> %2, <4 x i16>* %vector_ptr3, align 8
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%vector_ptr4 = bitcast i16* %scevgep2 to <4 x i16>*
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%vec4 = load <4 x i16>, <4 x i16>* %vector_ptr4, align 8
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%3 = sext <4 x i16> %vec4 to <4 x i32>
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%vec5 = mul <4 x i32> %3, %vec3
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%4 = trunc <4 x i32> %vec5 to <4 x i16>
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%vector_ptr5 = bitcast i16* %scevgep1 to <4 x i16>*
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store <4 x i16> %4, <4 x i16>* %vector_ptr5, align 8
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%5 = sext <4 x i16> %vec0 to <4 x i32>
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%vector_ptr6 = bitcast i16* %scevgep2 to <4 x i16>*
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%vec6 = load <4 x i16>, <4 x i16>* %vector_ptr6, align 8
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%6 = sext <4 x i16> %vec6 to <4 x i32>
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%vec7 = mul <4 x i32> %6, %5
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%vec8 = add <4 x i32> %vec7, %vec5
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%7 = trunc <4 x i32> %vec8 to <4 x i16>
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%vector_ptr7 = bitcast i16* %scevgep3 to <4 x i16>*
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store <4 x i16> %7, <4 x i16>* %vector_ptr7, align 8
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ret void
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}
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define void @func2(i16* %a, i16* %b, i16* %c) {
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; CHECK-LABEL: func2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: add r3, r1, #16
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; CHECK-NEXT: vldr d18, [r2, #16]
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; CHECK-NEXT: vld1.16 {d16}, [r3:64]
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; CHECK-NEXT: vmovl.u16 q8, d16
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; CHECK-NEXT: vaddw.s16 q10, q8, d18
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; CHECK-NEXT: vmovn.i32 d19, q10
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; CHECK-NEXT: vldr d20, [r0, #16]
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; CHECK-NEXT: vstr d19, [r0, #16]
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; CHECK-NEXT: vldr d19, [r2, #16]
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; CHECK-NEXT: vmull.s16 q11, d18, d19
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; CHECK-NEXT: vmovl.s16 q9, d19
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; CHECK-NEXT: vmla.i32 q11, q8, q9
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; CHECK-NEXT: vmovn.i32 d16, q11
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; CHECK-NEXT: vstr d16, [r1, #16]
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; CHECK-NEXT: vldr d16, [r2, #16]
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; CHECK-NEXT: vmlal.s16 q11, d16, d20
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; CHECK-NEXT: vaddw.s16 q8, q11, d20
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; CHECK-NEXT: vmovn.i32 d16, q8
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; CHECK-NEXT: vstr d16, [r0, #16]
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; CHECK-NEXT: bx lr
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entry:
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; The test case trying to vectorize the pseudo code below.
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; a[i] = b[i] + c[i];
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; b[i] = a[i] * c[i];
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; a[i] = b[i] + a[i] * c[i] + a[i];
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; Checking that vector load a[i] for "a[i] = b[i] + a[i] * c[i] + a[i]"
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; is scheduled before the first vector store to "a[i] = b[i] + c[i]".
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; Checking that there is no vector load a[i] scheduled between the first
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; vector store to a[i] and the vector add of a[i], otherwise the load of
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; a[i] will be polluted by the first vector store to a[i].
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; This test case check that both the chain and value of the new created
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; Load SDNode are updated during lowerMUL.
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%scevgep0 = getelementptr i16, i16* %a, i32 8
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%vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>*
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%vec0 = load <4 x i16>, <4 x i16>* %vector_ptr0, align 8
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%scevgep1 = getelementptr i16, i16* %b, i32 8
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%vector_ptr1 = bitcast i16* %scevgep1 to <4 x i16>*
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%vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
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%0 = zext <4 x i16> %vec1 to <4 x i32>
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%scevgep2 = getelementptr i16, i16* %c, i32 8
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%vector_ptr2 = bitcast i16* %scevgep2 to <4 x i16>*
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%vec2 = load <4 x i16>, <4 x i16>* %vector_ptr2, align 8
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%1 = sext <4 x i16> %vec2 to <4 x i32>
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%vec3 = add <4 x i32> %1, %0
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%2 = trunc <4 x i32> %vec3 to <4 x i16>
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%scevgep3 = getelementptr i16, i16* %a, i32 8
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%vector_ptr3 = bitcast i16* %scevgep3 to <4 x i16>*
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store <4 x i16> %2, <4 x i16>* %vector_ptr3, align 8
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%vector_ptr4 = bitcast i16* %scevgep2 to <4 x i16>*
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%vec4 = load <4 x i16>, <4 x i16>* %vector_ptr4, align 8
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%3 = sext <4 x i16> %vec4 to <4 x i32>
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%vec5 = mul <4 x i32> %3, %vec3
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%4 = trunc <4 x i32> %vec5 to <4 x i16>
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%vector_ptr5 = bitcast i16* %scevgep1 to <4 x i16>*
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store <4 x i16> %4, <4 x i16>* %vector_ptr5, align 8
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%5 = sext <4 x i16> %vec0 to <4 x i32>
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%vector_ptr6 = bitcast i16* %scevgep2 to <4 x i16>*
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%vec6 = load <4 x i16>, <4 x i16>* %vector_ptr6, align 8
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%6 = sext <4 x i16> %vec6 to <4 x i32>
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%vec7 = mul <4 x i32> %6, %5
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%vec8 = add <4 x i32> %vec7, %vec5
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%vec9 = add <4 x i32> %vec8, %5
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%7 = trunc <4 x i32> %vec9 to <4 x i16>
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%vector_ptr7 = bitcast i16* %scevgep3 to <4 x i16>*
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store <4 x i16> %7, <4 x i16>* %vector_ptr7, align 8
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ret void
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}
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