llvm-project/llvm/test/CodeGen/ARM/constant-islands-cfg.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv6m-apple-ios -run-pass=arm-cp-islands --verify-machine-dom-info %s -o - | FileCheck %s
--- |
; Function Attrs: minsize nounwind optsize uwtable
define arm_aapcscc double @test_split_cfg(double %a, double %b) local_unnamed_addr #0 {
ret double undef
}
...
---
name: test_split_cfg
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$r0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 48
offsetAdjustment: 0
maxAlignment: 4
adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
body: |
; CHECK-LABEL: name: test_split_cfg
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $r0
; CHECK: tCMPi8 killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.1, 0 /* CC::eq */, $cpsr
; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: successors: %bb.4(0x40000000)
; CHECK: liveins: $cpsr
; CHECK: tB %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: dead $r0 = SPACE 256, undef $r0
; CHECK: bb.3:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $pc
; CHECK: bb.4:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $pc
bb.0:
liveins: $r0
tCMPi8 killed $r0, 0, 14, $noreg, implicit-def $cpsr
tBcc %bb.2, 1, killed $cpsr
tB %bb.3, 14, $noreg
bb.1:
dead $r0 = SPACE 256, undef $r0
bb.2:
tPOP_RET 14, $noreg, def $pc
bb.3:
tPOP_RET 14, $noreg, def $pc
...