llvm-project/llvm/test/CodeGen
David Green ffc922ec35 [LSR] Attempt to increase the accuracy of LSR's setup cost
In some loops, we end up generating loop induction variables that look like:
  {(-1 * (zext i16 (%i0 * %i1) to i32))<nsw>,+,1}
As opposed to the simpler:
  {(zext i16 (%i0 * %i1) to i32),+,-1}
i.e we count up from -limit to 0, not the simpler counting down from limit to
0. This is because the scores, as LSR calculates them, are the same and the
second is filtered in place of the first. We end up with a redundant SUB from 0
in the code.

This patch tries to make the calculation of the setup cost a little more
thoroughly, recursing into the scev members to better approximate the setup
required. The cost function for comparing LSR costs is:

return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
                C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
       std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
                C2.ScaleCost, C2.ImmCost, C2.SetupCost);
So this will only alter results if none of the other variables turn out to be
different.

Differential Revision: https://reviews.llvm.org/D58770

llvm-svn: 355597
2019-03-07 13:44:40 +00:00
..
AArch64 [AArch64] Improve FP16 instruction selection for vector round and vector conver from half instructions 2019-03-06 20:30:06 +00:00
AMDGPU AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) 2019-03-07 00:54:04 +00:00
ARC
ARM [LSR] Attempt to increase the accuracy of LSR's setup cost 2019-03-07 13:44:40 +00:00
AVR [AVR] Insert unconditional branch when inserting MBBs between blocks with fallthrough 2019-01-21 04:32:02 +00:00
BPF [BPF] Do not generate BTF sections unnecessarily 2019-03-05 01:01:21 +00:00
Generic [AVR] Remove unneeded XFAILs from the Generic CodeGen tests 2019-01-20 11:16:58 +00:00
Hexagon [LSR] Attempt to increase the accuracy of LSR's setup cost 2019-03-07 13:44:40 +00:00
Inputs
Lanai
MIR [X86] Add FPCW as an implicit use on floating point load instructions. 2019-02-08 20:50:09 +00:00
MSP430 Enable integrated assembler on MSP430 by default. 2019-02-05 18:01:45 +00:00
Mips [MIPS GlobalISel] Fix mul operands 2019-03-07 13:28:29 +00:00
NVPTX [Codegen] fix typos in test case 2019-03-02 08:03:59 +00:00
PowerPC [PowerPC] Use real pointers instead of undef 2019-03-06 18:49:39 +00:00
RISCV [RISCV] Re-organise calling convention tests 2019-02-19 13:47:19 +00:00
SPARC
SystemZ [DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag. 2019-03-04 19:12:16 +00:00
Thumb [Thumb] Add some integer abs testcases for different typesizes. 2019-03-01 12:08:50 +00:00
Thumb2 [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs 2019-02-22 12:23:31 +00:00
WebAssembly [WebAssembly] Disable MachineBlockPlacement pass 2019-03-05 20:35:34 +00:00
WinCFGuard
WinEH Fix invalid target triples in tests. (NFC) 2019-03-04 23:37:41 +00:00
X86 [X86] Enable combineFMinNumFMaxNum for 512 bit vectors when AVX512 is enabled. 2019-03-07 06:30:19 +00:00
XCore