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AArch64
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[AArch64] Don't expand memcmp in strict align mode.
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2020-04-07 10:53:36 -07:00 |
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AMDGPU
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[AMDGPU] Implement copyPhysReg for 16 bit subregs
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2020-04-07 14:22:46 -07:00 |
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ARC
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…
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ARM
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[llvm] Fix missing FileCheck directive colons
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2020-04-06 09:59:08 -06:00 |
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AVR
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[AVR] Generalize the previous interrupt bugfix to signal handlers too
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2020-03-31 19:33:34 +13:00 |
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BPF
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[llvm] Fix missing FileCheck directive colons
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2020-04-06 09:59:08 -06:00 |
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Generic
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[X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.
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2020-03-26 14:10:20 -07:00 |
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Hexagon
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[llvm] Fix missing FileCheck directive colons
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2020-04-06 09:59:08 -06:00 |
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Inputs
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…
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Lanai
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…
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MIR
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AMDGPU: Assume f32 denormals are enabled by default
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2020-04-02 17:17:12 -04:00 |
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MSP430
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…
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Mips
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[llvm] Fix missing FileCheck directive colons
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2020-04-06 09:59:08 -06:00 |
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NVPTX
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[llvm] Fix missing FileCheck directive colons
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2020-04-06 09:59:08 -06:00 |
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PowerPC
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[NFC][PowerPC] Fix register class for patterns using XXPERMDIs
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2020-04-07 14:06:08 -05:00 |
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RISCV
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[LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG
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2020-04-01 15:51:26 +01:00 |
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SPARC
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…
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SystemZ
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[LoopDataPrefetch + SystemZ] Let target decide on prefetching for each loop.
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2020-04-02 14:57:46 +02:00 |
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Thumb
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[ARM] unwinding .pad instructions missing in execute-only prologue
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2020-04-07 11:51:59 +01:00 |
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Thumb2
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[ARM] unwinding .pad instructions missing in execute-only prologue
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2020-04-07 11:51:59 +01:00 |
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VE
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[VE] Update lea/load/store instructions
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2020-04-06 11:49:46 +02:00 |
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WebAssembly
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[WebAssembly] EmscriptenEHSjLj: Mark more functions as imported
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2020-04-06 21:27:31 -07:00 |
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WinCFGuard
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…
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WinEH
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…
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X86
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[X86][SSE] Add PTEST(AND(X,Y),AND(X,Y)) tests derived from PR42035 examples
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2020-04-07 17:58:54 +01:00 |
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XCore
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…
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