forked from OSchip/llvm-project
1492b70a03
A previous patch should have added pld and pstd and any support code in the backend that is required for prefixed load and store type operations. This patch adds a number of additional prefixed load and store type instructions for the future CPU. Differential Revision: https://reviews.llvm.org/D72577 |
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AArch64 | ||
AMDGPU | ||
ARC | ||
ARM | ||
Hexagon | ||
Lanai | ||
MSP430 | ||
Mips | ||
PowerPC | ||
RISCV | ||
Sparc | ||
SystemZ | ||
WebAssembly | ||
X86 | ||
XCore |