forked from OSchip/llvm-project
319 lines
11 KiB
LLVM
319 lines
11 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE \
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; RUN: --implicit-check-not xxswapd
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \
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; RUN: --implicit-check-not xxswapd
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -mattr=-vsx < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr < %s | FileCheck %s \
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; RUN: -check-prefix=CHECK-P9 --implicit-check-not xxswapd
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \
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; RUN: --implicit-check-not xxswapd
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd
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@x = common global <1 x i128> zeroinitializer, align 16
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@y = common global <1 x i128> zeroinitializer, align 16
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@a = common global i128 zeroinitializer, align 16
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@b = common global i128 zeroinitializer, align 16
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; VSX:
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; %a is passed in register 34
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; The value of 1 is stored in the TOC.
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; On LE, ensure the value of 1 is swapped before being used (using xxswapd).
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; VMX (no VSX):
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; %a is passed in register 2
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; The value of 1 is stored in the TOC.
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; No swaps are necessary when using P8 Vector instructions on LE
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define <1 x i128> @v1i128_increment_by_one(<1 x i128> %a) nounwind {
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%tmp = add <1 x i128> %a, <i128 1>
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ret <1 x i128> %tmp
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; FIXME: Seems a 128-bit literal is materialized by loading from the TOC. There
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; should be a better way of doing this.
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; CHECK-LE-LABEL: @v1i128_increment_by_one
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; CHECK-LE: lxvd2x [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-LE: xxswapd 35, [[VAL]]
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; CHECK-LE: vadduqm 2, 2, 3
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; CHECK-LE: blr
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; CHECK-P9-LABEL: @v1i128_increment_by_one
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; The below FIXME is due to the lowering for BUILD_VECTOR that will be fixed
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; in a subsequent patch.
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; FIXME: li [[R1:r[0-9]+]], 1
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; FIXME: li [[R2:r[0-9]+]], 0
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; FIXME: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]]
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; CHECK-P9: lxvx [[V1:v[0-9]+]]
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; CHECK-P9: vadduqm v2, v2, [[V1]]
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; CHECK-P9: blr
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; CHECK-BE-LABEL: @v1i128_increment_by_one
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; CHECK-BE: lxvd2x 35, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-BE-NOT: xxswapd
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; CHECK-BE: vadduqm 2, 2, 3
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; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}
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; CHECK-BE: blr
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; CHECK-NOVSX-LABEL: @v1i128_increment_by_one
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; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-NOT: stxvd2x {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX: lvx [[VAL:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-NOT: lxvd2x {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX: vadduqm 2, 2, [[VAL]]
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; CHECK-NOVSX: blr
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}
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; VSX:
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; %a is passed in register 34
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; %b is passed in register 35
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; No swaps are necessary when using P8 Vector instructions on LE
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; VMX (no VSX):
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; %a is passewd in register 2
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; %b is passed in register 3
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; On LE, do not need to swap contents of 2 and 3 because the lvx/stvx
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; instructions no not swap elements
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define <1 x i128> @v1i128_increment_by_val(<1 x i128> %a, <1 x i128> %b) nounwind {
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%tmp = add <1 x i128> %a, %b
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ret <1 x i128> %tmp
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; CHECK-LE-LABEL: @v1i128_increment_by_val
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; CHECK-LE-NOT: xxswapd
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; CHECK-LE: adduqm 2, 2, 3
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; CHECK-LE: blr
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; CHECK-BE-LABEL: @v1i128_increment_by_val
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; CHECK-BE-NOT: xxswapd {{[0-9]+}}, 34
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; CHECK-BE-NOT: xxswapd {{[0-9]+}}, 35
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; CHECK-BE-NOT: xxswapd 34, [[RESULT]]
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; CHECK-BE: adduqm 2, 2, 3
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; CHECK-BE: blr
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; CHECK-NOVSX-LABEL: @v1i128_increment_by_val
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; CHECK-NOVSX-NOT: xxswapd 34, [[RESULT]]
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; CHECK-NOVSX: adduqm 2, 2, 3
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; CHECK-NOVSX: blr
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}
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; Little Endian (VSX and VMX):
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; Lower 64-bits of %a are passed in register 3
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; Upper 64-bits of %a are passed in register 4
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; Increment lower 64-bits using addic (immediate value of 1)
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; Increment upper 64-bits using add zero extended
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; Results are placed in registers 3 and 4
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; Big Endian (VSX and VMX)
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; Lower 64-bits of %a are passed in register 4
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; Upper 64-bits of %a are passed in register 3
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; Increment lower 64-bits using addic (immediate value of 1)
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; Increment upper 64-bits using add zero extended
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; Results are placed in registers 3 and 4
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define i128 @i128_increment_by_one(i128 %a) nounwind {
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%tmp = add i128 %a, 1
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ret i128 %tmp
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; CHECK-LE-LABEL: @i128_increment_by_one
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; CHECK-LE: addic 3, 3, 1
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; CHECK-LE-NEXT: addze 4, 4
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; CHECK-LE: blr
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; CHECK-BE-LABEL: @i128_increment_by_one
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; CHECK-BE: addic 4, 4, 1
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; CHECK-BE-NEXT: addze 3, 3
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; CHECK-BE: blr
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; CHECK-LE-NOVSX-LABEL: @i128_increment_by_one
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; CHECK-LE-NOVSX: addic 3, 3, 1
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; CHECK-LE-NOVSX-NEXT: addze 4, 4
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; CHECK-LE-NOVSX: blr
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; CHECK-BE-NOVSX-LABEL: @i128_increment_by_one
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; CHECK-BE-NOVSX: addic 4, 4, 1
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; CHECK-BE-NOVSX-NEXT: addze 3, 3
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; CHECK-BE-NOVSX: blr
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}
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; Little Endian (VSX and VMX):
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; Lower 64-bits of %a are passed in register 3
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; Upper 64-bits of %a are passed in register 4
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; Lower 64-bits of %b are passed in register 5
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; Upper 64-bits of %b are passed in register 6
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; Add the lower 64-bits using addc on registers 3 and 5
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; Add the upper 64-bits using adde on registers 4 and 6
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; Registers 3 and 4 should hold the result
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; Big Endian (VSX and VMX):
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; Upper 64-bits of %a are passed in register 3
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; Lower 64-bits of %a are passed in register 4
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; Upper 64-bits of %b are passed in register 5
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; Lower 64-bits of %b are passed in register 6
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; Add the lower 64-bits using addc on registers 4 and 6
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; Add the upper 64-bits using adde on registers 3 and 5
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; Registers 3 and 4 should hold the result
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define i128 @i128_increment_by_val(i128 %a, i128 %b) nounwind {
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%tmp = add i128 %a, %b
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ret i128 %tmp
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; CHECK-LE-LABEL: @i128_increment_by_val
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; CHECK-LE: addc 3, 3, 5
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; CHECK-LE-NEXT: adde 4, 4, 6
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; CHECK-LE: blr
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; CHECK-BE-LABEL: @i128_increment_by_val
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; CHECK-BE: addc 4, 4, 6
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; CHECK-BE-NEXT: adde 3, 3, 5
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; CHECK-BE: blr
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; CHECK-LE-NOVSX-LABEL: @i128_increment_by_val
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; CHECK-LE-NOVSX: addc 3, 3, 5
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; CHECK-LE-NOVSX-NEXT: adde 4, 4, 6
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; CHECK-LE-NOVSX: blr
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; CHECK-BE-NOVSX-LABEL: @i128_increment_by_val
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; CHECK-BE-NOVSX: addc 4, 4, 6
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; CHECK-BE-NOVSX-NEXT: adde 3, 3, 5
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; CHECK-BE-NOVSX: blr
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}
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; Callsites for the routines defined above.
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; Ensure the parameters are loaded in the same order that is expected by the
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; callee. See comments for individual functions above for details on registers
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; used for parameters.
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define <1 x i128> @call_v1i128_increment_by_one() nounwind {
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%tmp = load <1 x i128>, <1 x i128>* @x, align 16
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%ret = call <1 x i128> @v1i128_increment_by_one(<1 x i128> %tmp)
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ret <1 x i128> %ret
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; CHECK-LE-LABEL: @call_v1i128_increment_by_one
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; CHECK-LE: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-LE: bl v1i128_increment_by_one
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; CHECK-LE: blr
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; CHECK-P9-LABEL: @call_v1i128_increment_by_one
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; CHECK-P9: lxvx
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; CHECK-P9: bl v1i128_increment_by_one
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; CHECK-P9: blr
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; CHECK-BE-LABEL: @call_v1i128_increment_by_one
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; CHECK-BE: lxvw4x 34, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}
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; CHECK-BE: bl v1i128_increment_by_one
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; CHECK-BE: blr
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; CHECK-NOVSX-LABEL: @call_v1i128_increment_by_one
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; CHECK-NOVSX: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-NOT: xxswapd {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX: bl v1i128_increment_by_one
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; CHECK-NOVSX: blr
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}
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define <1 x i128> @call_v1i128_increment_by_val() nounwind {
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%tmp = load <1 x i128>, <1 x i128>* @x, align 16
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%tmp2 = load <1 x i128>, <1 x i128>* @y, align 16
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%ret = call <1 x i128> @v1i128_increment_by_val(<1 x i128> %tmp, <1 x i128> %tmp2)
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ret <1 x i128> %ret
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; CHECK-LE-LABEL: @call_v1i128_increment_by_val
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; CHECK-LE: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-LE: lvx 3, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-LE: bl v1i128_increment_by_val
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; CHECK-LE: blr
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; CHECK-P9-LABEL: @call_v1i128_increment_by_val
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; CHECK-P9-DAG: lxvx v2
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; CHECK-P9-DAG: lxvx v3
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; CHECK-P9: bl v1i128_increment_by_val
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; CHECK-P9: blr
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; CHECK-BE-LABEL: @call_v1i128_increment_by_val
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; CHECK-BE-DAG: lxvw4x 35, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}
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; CHECK-BE-NOT: xxswapd 35, {{[0-9]+}}
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; CHECK-BE: bl v1i128_increment_by_val
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; CHECK-BE: blr
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; CHECK-NOVSX-LABEL: @call_v1i128_increment_by_val
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; CHECK-NOVSX-DAG: lvx 2, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-DAG: lvx 3, {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOVSX-NOT: xxswapd 34, {{[0-9]+}}
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; CHECK-NOVSX-NOT: xxswapd 35, {{[0-9]+}}
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; CHECK-NOVSX: bl v1i128_increment_by_val
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; CHECK-NOVSX: blr
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}
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define i128 @call_i128_increment_by_one() nounwind {
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%tmp = load i128, i128* @a, align 16
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%ret = call i128 @i128_increment_by_one(i128 %tmp)
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ret i128 %ret
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; %ret4 = call i128 @i128_increment_by_val(i128 %tmp2, i128 %tmp2)
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; CHECK-LE-LABEL: @call_i128_increment_by_one
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; CHECK-LE-DAG: ld 3, 0([[BASEREG:[0-9]+]])
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; CHECK-LE-DAG: ld 4, 8([[BASEREG]])
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; CHECK-LE: bl i128_increment_by_one
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; CHECK-LE: blr
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; CHECK-BE-LABEL: @call_i128_increment_by_one
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; CHECK-BE-DAG: ld 3, 0([[BASEREG:[0-9]+]])
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; CHECK-BE-DAG: ld 4, 8([[BASEREG]])
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; CHECK-BE: bl i128_increment_by_one
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; CHECK-BE: blr
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; CHECK-NOVSX-LABEL: @call_i128_increment_by_one
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; CHECK-NOVSX-DAG: ld 3, 0([[BASEREG:[0-9]+]])
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; CHECK-NOVSX-DAG: ld 4, 8([[BASEREG]])
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; CHECK-NOVSX: bl i128_increment_by_one
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; CHECK-NOVSX: blr
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}
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define i128 @call_i128_increment_by_val() nounwind {
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%tmp = load i128, i128* @a, align 16
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%tmp2 = load i128, i128* @b, align 16
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%ret = call i128 @i128_increment_by_val(i128 %tmp, i128 %tmp2)
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ret i128 %ret
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; CHECK-LE-LABEL: @call_i128_increment_by_val
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; CHECK-LE-DAG: ld 3, 0([[P1BASEREG:[0-9]+]])
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; CHECK-LE-DAG: ld 4, 8([[P1BASEREG]])
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; CHECK-LE-DAG: ld 5, 0([[P2BASEREG:[0-9]+]])
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; CHECK-LE-DAG: ld 6, 8([[P2BASEREG]])
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; CHECK-LE: bl i128_increment_by_val
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; CHECK-LE: blr
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; CHECK-BE-LABEL: @call_i128_increment_by_val
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; CHECK-BE-DAG: ld 3, 0([[P1BASEREG:[0-9]+]])
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; CHECK-BE-DAG: ld 4, 8([[P1BASEREG]])
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; CHECK-BE-DAG: ld 5, 0([[P2BASEREG:[0-9]+]])
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; CHECK-BE-DAG: ld 6, 8([[P2BASEREG]])
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; CHECK-BE: bl i128_increment_by_val
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; CHECK-BE: blr
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; CHECK-NOVSX-LABEL: @call_i128_increment_by_val
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; CHECK-NOVSX-DAG: ld 3, 0([[P1BASEREG:[0-9]+]])
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; CHECK-NOVSX-DAG: ld 4, 8([[P1BASEREG]])
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; CHECK-NOVSX-DAG: ld 5, 0([[P2BASEREG:[0-9]+]])
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; CHECK-NOVSX-DAG: ld 6, 8([[P2BASEREG]])
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; CHECK-NOVSX: bl i128_increment_by_val
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; CHECK-NOVSX: blr
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}
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