llvm-project/llvm/test/CodeGen/MIR
Geoff Berry e0bf52f394 [AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber.
Summary:
When searching for load/store instructions to pair/merge don't treat
writes to WZR/XZR as clobbers since they don't change the value read
from WZR/XZR (which is always 0).

Reviewers: mcrosier, junbuml, jmolloy, t.p.northover

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D26921

llvm-svn: 287592
2016-11-21 22:51:10 +00:00
..
AArch64 [AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber. 2016-11-21 22:51:10 +00:00
AMDGPU AMDGPU: Implement SGPR spilling with scalar stores 2016-11-13 18:20:54 +00:00
ARM MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
Generic [MIRPrinter] XFAIL test for powerpc 2016-11-18 20:08:05 +00:00
Hexagon [MIRParser] Parse lane masks for register live-ins 2016-10-12 21:06:45 +00:00
Lanai MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
Mips MIRParser: Use shorter cfi identifiers 2016-07-26 18:20:00 +00:00
NVPTX llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
PowerPC MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. 2016-08-24 01:32:41 +00:00
X86 [MIRPrinter] Print raw branch probabilities as expected by MIRParser 2016-11-18 19:37:24 +00:00