Benjamin Kramer ef479ea854 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. ... This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634		2012-05-29 19:05:25 +00:00
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enhanced.txt	Missed some register numbers.	2012-04-27 12:21:46 +00:00
intel-syntax.txt	Add -disassemble support for -show-inst and -show-encode capability llvm-mc. Also refactor so all MC paraphernalia are created once for all uses as much as possible.	2012-04-16 11:32:10 +00:00
invalid-VEX-vvvv.txt	Add test case for PR10851.	2011-09-14 04:36:54 +00:00
invalid-cmp-imm.txt	Add the tests that were supposed to go with r153935 that I forgot svn add	2012-04-06 07:09:59 +00:00
lit.local.cfg	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
simple-tests.txt	Change the second line of the test added for r152414 to use CHECK-NEXT.	2012-03-12 21:38:09 +00:00
truncated-input.txt	…
x86-32.txt	Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.	2012-05-29 19:05:25 +00:00
x86-64.txt	Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.	2012-05-29 19:05:25 +00:00