forked from OSchip/llvm-project
078572b6b1
Summary: Fix a bug discovered in an out-of-tree target where memoperands from pseudo-instructions that weren't part of the match were being merged into the result instructions as part of GIR_MergeMemOperands. This bug was caused by a change to the handling of State.MIs between rules when the state machine tables were fused into a single table. Previously, each rule would reset State.MIs using State.MIs.resize(1) but this is no longer done, as a result stale data is occasionally left in some elements of State.MIs. Most opcodes aren't affected by this but GIR_MergeMemOperands merges all memoperands from the intructions recorded in State.MIs into the result instruction. Suppose for example, we processed but rejected the following pattern: (signextend (load x)) at this point, State.MIs contains the signextend and the load. Now suppose we process and accept this pattern: (add x, y) at this point, State.MIs contains the add as well as the (now irrelevant) load. When GIR_MergeMemOperands is processed, the memoperands from that irrelevant load will be merged into the result instruction even though it was not part of the match. Bringing back the State.MIs.resize(1) would fix the problem but it would limit our ability to optimize the table in the future. Instead, this patch fixes the problem by explicitly stating which instructions should be merged into the result. There's no direct test case in this commit because a test case would be very brittle. However, at the time of writing this should fix the failures in http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/ as well as a failure in test/CodeGen/ARM/GlobalISel/arm-isel.ll when expensive checks are enabled. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: fhahn, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36094 llvm-svn: 309804 |
||
|---|---|---|
| .. | ||
| 2003-08-03-PassCode.td | ||
| 2006-09-18-LargeInt.td | ||
| 2010-03-24-PrematureDefaults.td | ||
| AnonDefinitionOnDemand.td | ||
| AsmPredicateCondsEmission.td | ||
| AsmVariant.td | ||
| BitOffsetDecoder.td | ||
| BitsInit.td | ||
| BitsInitOverflow.td | ||
| CStyleComment.td | ||
| ClassInstanceValue.td | ||
| Dag.td | ||
| DefmInherit.td | ||
| DefmInsideMultiClass.td | ||
| DuplicateFieldValues.td | ||
| FieldAccess.td | ||
| ForeachList.td | ||
| ForeachLoop.td | ||
| ForwardRef.td | ||
| GeneralList.td | ||
| GlobalISelEmitter.td | ||
| Include.inc | ||
| Include.td | ||
| IntBitInit.td | ||
| LazyChange.td | ||
| LetInsideMultiClasses.td | ||
| ListArgs.td | ||
| ListArgsSimple.td | ||
| ListConversion.td | ||
| ListManip.td | ||
| ListOfList.td | ||
| ListSlices.td | ||
| LoLoL.td | ||
| MultiClass.td | ||
| MultiClassDefName.td | ||
| MultiClassInherit.td | ||
| MultiPat.td | ||
| NestedForeach.td | ||
| Paste.td | ||
| RegisterBankEmitter.td | ||
| RegisterEncoder.td | ||
| SetTheory.td | ||
| SiblingForeach.td | ||
| Slice.td | ||
| String.td | ||
| SuperSubclassSameName.td | ||
| TargetInstrInfo.td | ||
| TargetInstrSpec.td | ||
| TemplateArgRename.td | ||
| Tree.td | ||
| TreeNames.td | ||
| TwoLevelName.td | ||
| UnsetBitInit.td | ||
| UnterminatedComment.td | ||
| ValidIdentifiers.td | ||
| cast-list-initializer.td | ||
| cast.td | ||
| defmclass.td | ||
| eq.td | ||
| eqbit.td | ||
| foreach.td | ||
| if-empty-list-arg.td | ||
| if.td | ||
| ifbit.td | ||
| intrinsic-long-name.td | ||
| intrinsic-varargs.td | ||
| lisp.td | ||
| list-element-bitref.td | ||
| listconcat.td | ||
| lit.local.cfg | ||
| math.td | ||
| nested-comment.td | ||
| pr8330.td | ||
| strconcat.td | ||
| subst.td | ||
| subst2.td | ||
| trydecode-emission.td | ||
| trydecode-emission2.td | ||
| trydecode-emission3.td | ||
| usevalname.td | ||