Asiri Rathnayake a0199b9a59 Add support for ARM modified-immediate assembly syntax. ... Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113		2014-12-02 10:53:20 +00:00
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AArch64	Condition codes AL and NV are invalid in the aliases that use	2014-06-10 13:11:35 +00:00
ARM	Add support for ARM modified-immediate assembly syntax.	2014-12-02 10:53:20 +00:00
Mips	The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.	2014-12-01 11:12:04 +00:00
PowerPC	[PowerPC] Add asm support for cache-inhibited ld/st instructions	2014-11-30 10:15:56 +00:00
Sparc	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	[SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA	2014-07-10 11:00:55 +00:00
X86	AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instruction	2014-10-26 09:52:24 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00