Tim Northover 28e0a6f7dd ARM: don't try to over-align large vectors as arguments. ... By default LLVM thinks very large vectors get aligned to their size when passed across functions. Unfortunately no-one told the ARM backend so it doesn't trigger stack realignment and so accesses can cause the usual misalignment issues (e.g. a data abort). This changes the ABI alignment to the stack alignment, which in practice (and as a bonus) also coincides with the alignment "natural" vectors get. llvm-svn: 331451		2018-05-03 12:54:25 +00:00
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AArch64	Rename invariant.group.barrier to launder.invariant.group	2018-05-03 11:03:01 +00:00
AMDGPU	Rename invariant.group.barrier to launder.invariant.group	2018-05-03 11:03:01 +00:00
ARC	…
ARM	ARM: don't try to over-align large vectors as arguments.	2018-05-03 12:54:25 +00:00
AVR	[AVR] Add a regression test for struct return lowering	2018-03-20 11:23:03 +00:00
BPF	bpf: fix incorrect SELECT_CC lowering	2018-04-03 03:56:37 +00:00
Generic	Rename invariant.group.barrier to launder.invariant.group	2018-05-03 11:03:01 +00:00
Hexagon	[LivePhysRegs] Remove registers clobbered by regmasks from the live set	2018-04-30 19:38:47 +00:00
Inputs	…
Lanai	…
MIR	MachineInst support mapping SDNode fast math flags for support in Back End code generation	2018-05-03 00:07:56 +00:00
MSP430	…
Mips	Reland r331175: "[mips] Fix the predicates of jump and branch and link instructions"	2018-05-01 13:06:49 +00:00
NVPTX	[NVPTX] Make the legalizer expand shufflevector of <2 x half>	2018-04-26 15:26:29 +00:00
Nios2	…
PowerPC	[PowerPC] Implement isMaskAndCmp0FoldingBeneficial	2018-05-02 23:55:23 +00:00
RISCV	[RISCV] Add remat.ll test case	2018-04-27 11:50:30 +00:00
SPARC	[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)	2018-05-01 19:26:15 +00:00
SystemZ	[SystemZ] Handle SADDO et.al. and ADD/SUBCARRY	2018-04-30 17:54:28 +00:00
Thumb	Reapply ARM: Do not spill CSR to stack on entry to noreturn functions	2018-04-07 10:57:03 +00:00
Thumb2	MachO: trap unreachable instructions	2018-04-13 22:25:20 +00:00
WebAssembly	[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor	2018-04-27 22:23:11 +00:00
WinCFGuard	…
WinEH	…
X86	[X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and YMM/ZMM scheduler classes	2018-05-03 10:31:20 +00:00
XCore	Use .set instead of = when printing assignment in assembly output	2018-03-27 16:44:41 +00:00