..
GlobalISel
GlobalISel: Use LLT in call lowering callbacks
2021-07-01 12:15:54 -04:00
32-bit-local-address-space.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
InlineAsmCrash.ll
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
README
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SRSRC-GIT-clobber-check.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
aa-points-to-constant-memory.ll
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acc-ldst.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
accvgpr-copy.mir
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks
2021-04-30 14:10:50 +01:00
add-debug.ll
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add.i16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
add.ll
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add.v2i16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
add3.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
add_i1.ll
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add_i64.ll
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add_i128.ll
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add_shl.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
addrspacecast-captured.ll
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addrspacecast-constantexpr.ll
[IR] Memory intrinsics are not unconditionally `nosync`
2021-05-21 03:40:59 +02:00
addrspacecast-initializer-unsupported.ll
[AMDGPU] Rename "LDS lowering" pass name.
2021-04-14 20:19:53 +05:30
addrspacecast-initializer.ll
Support addrspacecast initializers with isNoopAddrSpaceCast
2020-07-31 10:42:43 -04:00
addrspacecast.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
adjust-writemask-invalid-copy.ll
[AMDGPU] Added -mcpu to couple more tests. NFC.
2021-02-03 10:20:18 -08:00
adjust-writemask-vectorized.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
agpr-csr.ll
AMDGPU: Add missing runline to test
2021-04-29 20:59:22 -04:00
agpr-register-count.ll
[AMDGPU][IndirectCalls] Fix register usage propagation for indirect/external calls
2021-06-12 11:59:34 +05:30
agpr-remat.ll
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
alignbit-pat.ll
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alloc-aligned-tuples-gfx90a.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
alloc-aligned-tuples-gfx908.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
alloc-all-regs-reserved-in-class.mir
RegAlloc: Fix assert if all registers in class reserved
2021-01-31 11:10:04 -05:00
alloca.ll
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always-uniform.ll
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amd.endpgm.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
amdgcn-ieee.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
amdgcn-load-offset-from-reg.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
amdgcn.bitcast.ll
[AMDGPU] Fix crash when dag-combining bitcast
2020-08-13 10:23:13 +08:00
amdgcn.private-memory.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdgpu-alias-analysis.ll
[NewPM][AMDGPU] Make amdgpu-aa work with NewPM
2021-01-04 12:36:27 -08:00
amdgpu-codegenprepare-fdiv.ll
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amdgpu-codegenprepare-fold-binop-select.ll
Reapply [ConstantFold] Fold more operations to poison
2021-05-13 16:04:12 +02:00
amdgpu-codegenprepare-foldnegate.ll
[AMDGPU] [CodeGen] Fold negate llvm.amdgcn.class into test mask
2021-06-18 13:04:12 -06:00
amdgpu-codegenprepare-i16-to-i32.ll
[AMDGPU] Update generated checks. NFC.
2021-06-18 10:49:02 +01:00
amdgpu-codegenprepare-idiv.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
amdgpu-codegenprepare-mul24.ll
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amdgpu-function-calls-option.ll
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amdgpu-inline.ll
[AMDGPU] Do not check max-bb for a single block callee
2021-03-01 19:48:50 -08:00
amdgpu-late-codegenprepare.ll
AMDGPU: Fix assert on constant load from addrspacecasted pointer
2021-05-11 20:12:20 -04:00
amdgpu-mul24-knownbits.ll
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amdgpu-reloc-const.ll
[llvm-readobj] - For SHT_REL relocations, don't display an addend.
2020-12-14 12:03:00 +03:00
amdgpu-shader-calling-convention.ll
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amdgpu-unroll-threshold.ll
[BasicAA] Rename deprecated -basicaa to -basic-aa
2020-06-26 20:41:37 -07:00
amdgpu.private-memory.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
amdgpu.work-item-intrinsics.deprecated.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdhsa-trap-num-sgprs.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
amdpal-callable.ll
[AMDGPU] Set optional PAL metadata
2021-07-06 11:58:00 +02:00
amdpal-cs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-elf.ll
[test] Change -t to --syms and -s to -S for llvm-readobj RUN lines
2021-06-29 11:50:31 -07:00
amdpal-es.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-gs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-hs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-ls.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-cs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-default.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-denormal.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-dx10-clamp.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-es.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-gs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-hs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-ieee.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-ls.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-ps.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-psenable.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-vs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-ps.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-psenable.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-vs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal.ll
[AMDGPU] Emit new pal metadata by default
2020-10-26 10:16:17 +01:00
amdpal_scratch_mergedshader.ll
…
and-gcn.ll
…
and.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
and_or.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
andorbitset.ll
AMDGPU: Fix verifier error with undef source producing s_bitset*
2020-08-05 14:42:20 -04:00
andorn2.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
andorxorinvimm.ll
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annotate-kernel-features-hsa-call.ll
[AMDGPU] Remove error check for indirect calls and add missing queue-ptr
2021-04-20 00:35:17 +05:30
annotate-kernel-features-hsa.ll
AMDGPU: Add IntrWillReturn to intrinsic definitions
2020-06-18 15:38:10 -04:00
annotate-kernel-features.ll
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annotate-noclobber.ll
AMDGPU: Annotate amdgpu.noclobber for global loads only
2021-01-05 14:47:19 -08:00
anonymous-gv.ll
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any_extend_vector_inreg.ll
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anyext.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
are-loads-from-same-base-ptr.ll
…
array-ptr-calc-i32.ll
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array-ptr-calc-i64.ll
…
ashr.v2i16.ll
…
asm-printer-check-vcc.mir
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
at-least-one-def-value-assert.mir
…
atomic_cmp_swap_local.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
atomic_load_add.ll
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atomic_load_local.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
atomic_load_sub.ll
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atomic_optimizations_buffer.ll
[AMDGPU] Remove weird target triples from tests. NFC.
2021-03-19 16:48:32 +00:00
atomic_optimizations_global_pointer.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
atomic_optimizations_local_pointer.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
atomic_optimizations_pixelshader.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
atomic_optimizations_raw_buffer.ll
[AMDGPU] Remove weird target triples from tests. NFC.
2021-03-19 16:48:32 +00:00
atomic_optimizations_struct_buffer.ll
[AMDGPU] Remove weird target triples from tests. NFC.
2021-03-19 16:48:32 +00:00
atomic_store_local.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
atomicrmw-nand.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
attr-amdgpu-flat-work-group-size-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
attr-amdgpu-flat-work-group-size-vgpr-limit.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
attr-amdgpu-flat-work-group-size.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
attr-amdgpu-num-sgpr.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
attr-amdgpu-num-vgpr.ll
…
attr-amdgpu-waves-per-eu.ll
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attr-unparseable.ll
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barrier-elimination.ll
[AMDGPU][GlobalISel] Eliminate barrier if workgroup size is not greater than wavefront size
2020-08-26 13:47:51 +01:00
basic-branch.ll
[AMDGPU] Use lowercase for subtarget feature names in RUN lines
2020-10-13 09:02:09 +01:00
basic-call-return.ll
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basic-loop.ll
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bfe-combine.ll
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bfe-patterns.ll
[AMDGPU] Make bfe patterns divergence-aware
2020-10-05 09:55:10 +01:00
bfe_uint.ll
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bfi_int.ll
[AMDGPU] Add alignment check for v3 to v4 load type promotion
2020-11-01 12:05:34 +05:30
bfm.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
big_alu.ll
…
bitcast-constant-to-vector.ll
…
bitcast-v4f16-v4i16.ll
…
bitcast-vector-extract.ll
…
bitreverse-inline-immediates.ll
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bitreverse.ll
[AMDGPU] Better codegen for i64 bitreverse
2021-02-26 15:51:36 +00:00
br_cc.f16.ll
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branch-condition-and.ll
[AMDGPU] Keep skip branch for ds instructions
2021-03-05 12:34:09 +01:00
branch-relax-bundle.ll
…
branch-relax-spill.ll
…
branch-relaxation-debug-info.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
branch-relaxation-gfx10-branch-offset-bug.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
branch-relaxation-inst-size-gfx10.ll
…
branch-relaxation.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
branch-uniformity.ll
…
break-smem-soft-clauses.mir
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
break-vmem-soft-clauses.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
bswap.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
buffer-intrinsics-mmo-offsets.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
buffer-schedule.ll
…
bug-sdag-scheduler-cycle.ll
…
bug-vopc-commute.ll
…
build-vector-insert-elt-infloop.ll
…
build-vector-packed-partial-undef.ll
…
build_vector.ll
…
bundle-latency.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
bypass-div.ll
[AMDGPU] Add Optimize VGPR LiveRange Pass.
2021-06-21 15:25:55 +08:00
byval-frame-setup.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
call-argument-types.ll
[TargetLowering] Only inspect attributes in the arguments for ArgListEntry
2021-05-18 14:30:22 -07:00
call-constant.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
call-constexpr.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
call-encoding.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
call-graph-register-usage.ll
[AMDGPU][IndirectCalls] Fix register usage propagation for indirect/external calls
2021-06-12 11:59:34 +05:30
call-preserved-registers.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
call-return-types.ll
AMDGPU: Improve <2 x i24> arguments and return value handling
2020-09-16 11:21:56 -04:00
call-skip.ll
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call-to-kernel-undefined.ll
…
call-to-kernel.ll
…
call-waitcnt.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
call-waw-waitcnt.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
call_fs.ll
…
callee-frame-setup.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
callee-special-input-sgprs-fixed-abi.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
callee-special-input-sgprs.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
callee-special-input-vgprs-packed.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
callee-special-input-vgprs.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
calling-conventions.ll
…
captured-frame-index.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
carryout-selection.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
cayman-loop-bug.ll
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cc-sgpr-limit.ll
…
cc-sgpr-over-limit.ll
…
cc-update.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
cf-loop-on-constant.ll
[LSR] Fix for pre-indexed generated constant offset
2021-04-15 16:44:42 +01:00
cf-stack-bug.ll
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cf_end.ll
…
cgp-addressing-modes-flat.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
cgp-addressing-modes-gfx908.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
cgp-addressing-modes-gfx1030.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
cgp-addressing-modes.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
cgp-bitfield-extract.ll
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chain-hi-to-lo.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
change-scc-to-vcc.mir
[AMDGPU] Update SCC defs to VCC when uses are changed to VCC
2021-05-14 18:05:05 -04:00
clamp-modifier.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
clamp-omod-special-case.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
clamp.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
cluster-flat-loads-postra.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
cluster-flat-loads.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
cluster_stores.ll
[AMDGPU] Do not clause NSA instructions
2021-05-14 12:54:56 +09:00
cmp_shrink.mir
[AMDGPU] Avoid using s_cmpk when src0 is not register
2020-07-14 09:05:53 +01:00
cndmask-no-def-vcc.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
coalesce-identity-copies-undef-subregs.mir
RegisterCoalescer: Prune undef subranges from copy pairs in loops
2021-02-03 13:42:53 -05:00
coalesce-vgpr-alignment.ll
AMDGPU: Remove special case in shouldCoalesce
2021-02-24 14:49:44 -05:00
coalescer-extend-pruned-subrange.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
coalescer-identical-values-undef.mir
…
coalescer-removepartial-extend-undef-subrange.mir
[RegisterCoalescer] Pass Undefs to extendToIndices()
2020-09-29 08:14:24 +08:00
coalescer-subranges-another-copymi-not-live.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
coalescer-subranges-another-prune-error.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
coalescer-subranges-prune-kill-copy.mir
…
coalescer-subreg-join.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
coalescer-subregjoin-fullcopy.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
coalescer-with-subregs-bad-identical.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
coalescer_distribute.ll
…
coalescer_remat.ll
[AMDGPU] Switch AnnotateUniformValues to MemorySSA
2021-05-05 18:34:41 -07:00
coalescing-subreg-was-undef-but-became-def.mir
…
coalescing-with-subregs-in-loop-bug.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
coalescing_makes_lanes_undef.mir
[RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining
2020-09-24 17:37:03 +03:00
code-object-v3.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
codegen-prepare-addrmode-sext.ll
…
collapse-endcf-broken.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
collapse-endcf.ll
[AMDGPU] Add Optimize VGPR LiveRange Pass.
2021-06-21 15:25:55 +08:00
collapse-endcf.mir
[AMDGPU] Remove fix up operand from SI_ELSE
2020-10-20 19:15:21 +09:00
collapse-endcf2.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
combine-add-zext-xor.ll
[AMDGPU] Fix a miscompile with S_ADD/S_SUB
2021-02-17 12:24:58 +01:00
combine-and-sext-bool.ll
…
combine-cond-add-sub.ll
…
combine-ftrunc.ll
…
combine-sreg64-inits.mir
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
combine_vloads.ll
…
comdat.ll
…
commute-compares.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
commute-shifts.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
commute-vop3.mir
[AMDGPU] Make some VOP3 insts commutable
2021-04-28 13:59:08 -04:00
commute_modifiers.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
complex-folding.ll
…
computeKnownBits-scalar-to-vector-crash.ll
…
computeNumSignBits-mul.ll
…
concat_vectors.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
constant-address-space-32bit.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
constant-fold-imm-immreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
constant-fold-mi-operands.ll
…
control-flow-fastregalloc.ll
[AMDGPU] Save VGPR of whole wave when spilling
2021-04-12 11:01:38 +02:00
control-flow-optnone.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
convergent-inlineasm.ll
…
copy-illegal-type.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
copy-overlap-vgpr-kill.mir
AMDGPU: Don't kill super-register with overlapping copy
2020-10-16 09:34:35 -04:00
copy-to-reg.ll
…
copy_phys_vgpr64.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
couldnt-join-subrange-3.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
cross-block-use-is-not-abi-copy.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
cse-phi-incoming-val.ll
…
csr-gfx10.ll
[AMDGPU] Use pseudo instructions for readlane/writelane
2020-10-29 16:00:53 +00:00
csr-sgpr-spill-live-ins.mir
AMDGPU: Add spilled CSR SGPRs to entry block live ins
2020-12-22 21:55:59 -05:00
ctlz.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
ctlz_zero_undef.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
ctpop.ll
…
ctpop16.ll
…
ctpop64.ll
…
cttz_zero_undef.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
cube.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
cvt_f32_ubyte.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
cvt_flr_i32_f32.ll
…
cvt_rpi_i32_f32.ll
…
dag-divergence-atomic.ll
[AMDGPU] Update gfx90a memory model support
2021-04-07 22:17:58 +00:00
dag-divergence.ll
…
dagcomb-shuffle-vecextend-non2.ll
…
dagcombine-reassociate-bug.ll
…
dagcombine-select.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
dagcombine-setcc-select.ll
…
dagcombiner-bug-illegal-vec4-int-to-fp.ll
…
dbg-value-ends-sched-region.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
dce-disjoint-intervals.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
dead-lane.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
dead-machine-elim-after-dead-lane.ll
…
dead_copy.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
debug-value-scheduler-crash.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
debug-value.ll
VirtRegMap: Preserve LiveDebugVariables
2021-05-27 10:40:14 -04:00
debug-value2.ll
…
debug.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
debug_frame.ll
[MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling
2021-05-06 04:53:45 +05:30
default-fp-mode.ll
…
detect-dead-lanes.mir
…
direct-indirect-call.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
directive-amdgcn-target.ll
[AMDGPU] Add gfx1035 target
2021-06-24 14:32:41 -04:00
disable_form_clauses.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
disconnected-predset-break-bug.ll
…
div_i128.ll
AMDGPU: Have a few selection failure tests check both paths
2020-08-24 17:46:31 -04:00
diverge-extra-formal-args.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
diverge-interp-mov-lower.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
diverge-switch-default.ll
…
divergence-at-use.ll
…
divergent-branch-uniform-condition.ll
…
divrem24-assume.ll
…
dpp64_combine.ll
[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
2021-02-22 14:59:40 +03:00
dpp64_combine.mir
AMDGPU: Add even aligned VGPR/AGPR register classes
2021-02-24 14:49:37 -05:00
dpp_combine.ll
[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
2021-02-22 14:59:40 +03:00
dpp_combine.mir
[AMDGPU] GCNDPPCombine: don't shrink V_ADD_CO_U32 if carry out is used
2021-04-20 09:17:52 +01:00
drop-mem-operand-move-smrd.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
ds-alignment.ll
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
ds-combine-large-stride.ll
[AMDGPU] Better selection of base offset when merging DS reads/writes
2021-02-11 17:46:09 +00:00
ds-combine-with-dependence.ll
[amdgpu] Enable use of AA during codegen.
2020-10-27 09:46:23 -04:00
ds-negative-offset-addressing-mode-loop.ll
…
ds-sub-offset.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
ds_gws_align.ll
[AMDGPU] All GWS instructions need aligned VGPR on gfx90a
2021-06-01 17:08:03 -07:00
ds_read2.ll
[AMDGPU] Propagate LDS align into to instructions
2021-06-23 00:57:16 -07:00
ds_read2_offset_order.ll
[AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering.
2021-06-07 18:00:41 +05:30
ds_read2_superreg.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
ds_read2st64.ll
AMDGPU: Match global saddr addressing mode
2020-08-17 15:28:14 -04:00
ds_write2.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
ds_write2st64.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
duplicate-attribute-indirect.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
dynamic_stackalloc.ll
…
early-if-convert-cost.ll
…
early-if-convert.ll
…
early-inline-alias.ll
…
early-inline.ll
…
early-tailduplicator-nophis.mir
…
early-term.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
elf-header-flags-mach.ll
[AMDGPU] Add gfx1035 target
2021-06-24 14:32:41 -04:00
elf-header-flags-sramecc.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
elf-header-flags-xnack.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
elf-header-osabi.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
elf-notes.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
elf.ll
…
elf.metadata.ll
…
elf.r600.ll
…
else.ll
…
empty-function.ll
…
enable-no-signed-zeros-fp-math.ll
…
endcf-loop-header.ll
…
endpgm-dce.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
enqueue-kernel.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
exceed-max-sgprs.ll
Improve the diagnostic of DiagnosticInfoResourceLimit (and warn-stack-size in particular)
2021-06-22 09:55:20 -07:00
expand-atomicrmw-syncscope.ll
[AMDGPU] Update gfx90a memory model support
2021-04-07 22:17:58 +00:00
expand-scalar-carry-out-select-user.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
expand-si-indirect.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
extend-bit-ops-i16.ll
…
extload-align.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
extload-private.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
extload.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
extra-sroa-after-unroll.ll
[NFC][AMDGPU] Clean up some lit test prefixes
2020-11-11 17:12:37 +00:00
extract-load-i1.ll
[DAGCombine] Fix bug in load scalarization
2020-11-04 19:02:40 +00:00
extract-lowbits.ll
…
extract-subvector-equal-length.ll
…
extract-subvector.ll
…
extract-vector-elt-build-vector-combine.ll
…
extract_subvector_vec4_vec3.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
extract_vector_dynelt.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
extract_vector_elt-f16.ll
…
extract_vector_elt-f64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
extract_vector_elt-i8.ll
…
extract_vector_elt-i16.ll
[AMDGPU] Remove cpol, tfe, and swz from MUBUF patterns
2021-03-18 14:36:04 -07:00
extract_vector_elt-i64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
extractelt-to-trunc.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
fabs.f16.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
fabs.f64.ll
…
fabs.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
fadd-fma-fmul-combine.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
fadd.f16.ll
…
fadd.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
fadd64.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
fail-select-buffer-atomic-fadd.ll
[AMDGPU] Unify intrinsic ret/nortn interface
2020-09-15 15:26:42 -07:00
fast-ra-kills-vcc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fast-regalloc-bundles.mir
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fast-unaligned-load-store.global.ll
[AMDGPU] Make some VOP3 insts commutable
2021-04-28 13:59:08 -04:00
fast-unaligned-load-store.private.ll
[AMDGPU] Make some VOP3 insts commutable
2021-04-28 13:59:08 -04:00
fastregalloc-illegal-subreg-physreg.mir
Reapply "RegAllocFast: Rewrite and improve"
2020-09-30 10:35:25 -04:00
fastregalloc-self-loop-heuristic.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fcanonicalize-elimination.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
fcanonicalize.f16.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
fcanonicalize.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
fceil.ll
…
fceil64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
fcmp.ll
…
fcmp64.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
fconst64.ll
…
fcopysign.f16.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fcopysign.f32.ll
…
fcopysign.f64.ll
…
fdiv-nofpexcept.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
fdiv.f16.ll
AMDGPU: Match global saddr addressing mode
2020-08-17 15:28:14 -04:00
fdiv.f64.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
fdiv.ll
[DAGCombiner] Require ninf for division estimation
2020-06-14 22:58:22 +08:00
fdiv32-to-rcp-folding.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
fdot2.ll
…
fence-barrier.ll
…
fence-lds-read2-write2.ll
[AMDGPU] Better selection of base offset when merging DS reads/writes
2021-02-11 17:46:09 +00:00
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
fexp.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
ffloor.f64.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
ffloor.ll
…
fix-frame-ptr-reg-copy-livein.ll
[AMDGPU] Mark epilog restores as frame-destroy
2021-02-02 10:24:37 +01:00
fix-sgpr-copies.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fix-vgpr-copies.mir
…
fix-wwm-vgpr-copy.ll
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
2021-03-03 09:33:57 +01:00
flat-address-space.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
flat-error-unsupported-gpu-hsa.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
flat-for-global-subtarget-feature.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
flat-load-clustering.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
flat-offset-bug.ll
…
flat-scratch-fold-fi.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
flat-scratch-reg.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
flat-scratch.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
flat_atomics.ll
…
flat_atomics_i64.ll
…
floor.ll
…
fma-combine.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
fma.f64.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
fma.ll
…
fmac.sdwa.ll
…
fmad-formation-fmul-distribute-denormal-mode.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
fmad.ll
…
fmax.ll
…
fmax3.f64.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
fmax3.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
fmax_legacy.f16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
fmax_legacy.f64.ll
[AMDGPU] Optimize waitcnt insertion for flat memory operations
2020-10-20 22:55:12 +00:00
fmax_legacy.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fmaxnum.f64.ll
…
fmaxnum.ll
…
fmaxnum.r600.ll
…
fmed3.ll
…
fmin.ll
…
fmin3.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
fmin_fmax_legacy.amdgcn.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fmin_legacy.f16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
fmin_legacy.f64.ll
[AMDGPU] Optimize waitcnt insertion for flat memory operations
2020-10-20 22:55:12 +00:00
fmin_legacy.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fminnum.f64.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fminnum.ll
…
fminnum.r600.ll
…
fmul-2-combine-multi-use.ll
…
fmul.f16.ll
…
fmul.ll
…
fmul64.ll
…
fmuladd.f16.ll
[DAGCombine] reassoc flag shouldn't enable contract
2021-06-21 21:15:43 +00:00
fmuladd.f32.ll
[DAGCombine] reassoc flag shouldn't enable contract
2021-06-21 21:15:43 +00:00
fmuladd.f64.ll
[DAGCombine] reassoc flag shouldn't enable contract
2021-06-21 21:15:43 +00:00
fmuladd.v2f16.ll
[DAGCombine] reassoc flag shouldn't enable contract
2021-06-21 21:15:43 +00:00
fnearbyint.ll
…
fneg-combines.ll
AMDGPU: Fix infinite loop in DAG combine with fneg + fma
2021-06-18 19:09:03 -04:00
fneg-combines.si.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fneg-fabs.f16.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fneg-fabs.f64.ll
…
fneg-fabs.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fneg-fold-legalize-dag-increase-insts.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
fneg.f16.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
fneg.f64.ll
…
fneg.ll
…
fold-cndmask-wave32.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
fold-cndmask.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
fold-fi-mubuf.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
fold-fi-operand-shrink.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-fmul-to-neg-abs.ll
…
fold-imm-copy.mir
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
fold-imm-f16-f32.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fold-immediate-operand-shrink-with-carry.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-immediate-operand-shrink.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-immediate-output-mods.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
fold-implicit-operand.mir
…
fold-multiple.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
fold-operands-order.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
fold-operands-remove-m0-redef.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fold-over-exec.mir
…
fold-readlane.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
fold-reload-into-exec.mir
[AMDGPU] Save all lanes for reserved VGPRs
2021-02-04 09:56:36 +01:00
fold-reload-into-m0.mir
[AMDGPU] Save all lanes for reserved VGPRs
2021-02-04 09:56:36 +01:00
fold-sgpr-copy.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
fold-sgpr-multi-imm.mir
…
fold-vgpr-copy.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
fold_16bit_imm.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
fold_acc_copy_into_valu.mir
…
force-alwaysinline-lds-global-address-codegen.ll
[AMDGPU] Disable forceful inline of non-kernel functions which use LDS.
2021-04-15 09:12:56 +05:30
force-alwaysinline-lds-global-address.ll
[AMDGPU] Disable forceful inline of non-kernel functions which use LDS.
2021-04-15 09:12:56 +05:30
fp-atomic-to-s_denormmode.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fp-classify.ll
…
fp16_to_fp32.ll
…
fp16_to_fp64.ll
…
fp32_to_fp16.ll
…
fp64-atomics-gfx90a.ll
[AMDGPU] Update gfx90a memory model support
2021-06-30 04:05:22 +00:00
fp_to_sint.f64.ll
…
fp_to_sint.ll
[amdgpu] Improve the from f32 to i64.
2021-06-19 12:46:48 -04:00
fp_to_uint.f64.ll
…
fp_to_uint.ll
[amdgpu] Improve the from f32 to i64.
2021-06-19 12:46:48 -04:00
fpext-free.ll
[DAGCombine] Check reassoc flags in aggressive fsub fusion
2021-06-23 13:59:40 +00:00
fpext.f16.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fpext.ll
…
fpow.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
fptosi.f16.ll
[AMDGPU] Select V_CVT_*16_F16 more often
2021-05-05 08:57:51 +01:00
fptoui.f16.ll
[AMDGPU] Select V_CVT_*16_F16 more often
2021-05-05 08:57:51 +01:00
fptrunc.f16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
fptrunc.ll
…
fract.f64.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fract.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
frame-index-elimination.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
frame-lowering-entry-all-sgpr-used.mir
…
frame-lowering-fp-adjusted.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
frame-setup-without-sgpr-to-vgpr-spills.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
frem.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
fshl.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
fshr.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
fsqrt.f64.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
fsqrt.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
fsub.f16.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fsub.ll
…
fsub64.ll
…
ftrunc.f64.ll
…
ftrunc.ll
…
function-args.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
function-call-relocs.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
function-returns.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
gds-atomic.ll
…
gep-address-space.ll
…
gfx-callable-argument-types.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
gfx-callable-preserved-registers.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
gfx-callable-return-types.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
gfx10-vop-literal.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
gfx90a-enc.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
gfx902-without-xnack.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
global-atomics-fp-wrong-subtarget.ll
AMDGPU: Restore atomic fp feature on FP atomic instruction definitions
2021-04-22 21:32:01 -04:00
global-atomics-fp.ll
[AMDGPU] Move atomic expand past infer address spaces
2021-07-06 15:53:32 -07:00
global-constant.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
global-directive.ll
…
global-extload-i16.ll
…
global-load-saddr-to-vaddr.ll
AMDGPU: Fix assert when rewriting saddr d16 loads
2021-05-14 13:24:19 -04:00
global-saddr-atomics.gfx908.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
global-saddr-atomics.gfx1030.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
global-saddr-atomics.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
global-saddr-load.ll
[AMDGPU] Improve global SADDR selection
2021-05-05 14:44:21 -07:00
global-saddr-store.ll
[AMDGPU] Don't check for VMEM hazards on GFX10
2021-03-04 21:44:56 +00:00
global-smrd-unknown.ll
[AMDGPU] Switch AnnotateUniformValues to MemorySSA
2021-05-05 18:34:41 -07:00
global-variable-relocs.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
global_atomics.ll
[AMDGPU] Improve global SADDR selection
2021-05-05 14:44:21 -07:00
global_atomics_i64.ll
[AMDGPU] Improve global SADDR selection
2021-05-05 14:44:21 -07:00
global_smrd.ll
[amdgpu] Enable use of AA during codegen.
2020-10-27 09:46:23 -04:00
global_smrd_cfg.ll
[AA] Split up LocationSize::unknown()
2020-11-26 18:39:55 +01:00
greedy-broken-ssa-verifier-error.mir
RegAlloc: Clear isSSA
2020-10-28 12:02:16 -04:00
gv-const-addrspace.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
gv-offset-folding.ll
…
gws-hazards.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
half.ll
[AMDGPU] Don't cluster stores
2020-09-14 13:40:17 +01:00
hard-clauses.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
hazard-buffer-store-v-interp.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-hidden-bundle.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-in-bundle.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-inlineasm.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-kill.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-pass-ordering.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-recognizer-meta-insts.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard.mir
…
high-bits-zeroed-16-bit-ops.mir
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
hip.extern.shared.array.ll
[amdgpu] Add codegen support for HIP dynamic shared memory.
2020-08-20 21:29:18 -04:00
hoist-cond.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
hsa-default-device.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-fp-mode.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-func-align.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-func.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-globals.ll
[AMDGPU] Corrected directive to use for ELF weak refs
2020-09-16 18:51:26 +03:00
hsa-group-segment.ll
…
hsa-metadata-deduce-ro-arg-v3.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-deduce-ro-arg.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-enqueue-kernel-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-enqueue-kernel.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
hsa-metadata-from-llvm-ir-full-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-from-llvm-ir-full.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
hsa-metadata-hidden-args-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-hidden-args.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
hsa-metadata-hostcall-absent-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-hostcall-absent.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-hostcall-present-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-hostcall-present.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-images-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-images.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
hsa-metadata-invalid-ocl-version-1-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-1.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-invalid-ocl-version-2-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-2.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-invalid-ocl-version-3-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-3.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-kernel-code-props-v3.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
hsa-metadata-kernel-code-props.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
hsa-metadata-wavefrontsize.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-note-no-func.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa.ll
[test] Change -t to --syms and -s to -S for llvm-readobj RUN lines
2021-06-29 11:50:31 -07:00
huge-number-operand-folds.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
huge-private-buffer.ll
…
i1-copies-rpo.mir
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks
2021-04-30 14:10:50 +01:00
i1-copy-from-loop.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
i1-copy-implicit-def.ll
…
i1-copy-phi-uniform-branch.ll
…
i1-copy-phi.ll
…
i1_copy_phi_with_phi_incoming_value.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
i8-to-double-to-float.ll
…
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
…
icmp64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
idiv-licm.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
idot2.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
idot4s.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
idot4u.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
idot8s.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
idot8u.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
illegal-sgpr-to-vgpr-copy.ll
…
image-attributes.ll
…
image-load-d16-tfe.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
image-resource-id.ll
…
image-sample-waterfall.ll
AMDGPU: Implement waterfall loop for MIMG instructions with 256-bit SRsrc
2020-08-18 16:27:36 -07:00
image-schedule.ll
…
image_ls_mipmap_zero.ll
…
img-nouse-adjust.ll
…
imm.ll
…
imm16.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
immv216.ll
[AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P
2021-03-02 13:02:25 +03:00
implicit-def-muse.ll
…
indirect-addressing-si-gfx9.ll
AMDGPU: Fix assert on m0_lo16/m0_hi16
2021-06-18 18:48:53 -04:00
indirect-addressing-si-noopt.ll
…
indirect-addressing-si-pregfx9.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
indirect-addressing-si.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
indirect-addressing-term.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
indirect-call.ll
[AMDGPU][IndirectCalls] Fix register usage propagation for indirect/external calls
2021-06-12 11:59:34 +05:30
indirect-private-64.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
infer-addrpace-pipeline.ll
[NewPM] Port infer-address-spaces
2020-12-28 19:58:12 -08:00
infer-uniform-load-shader.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
infinite-loop-evergreen.ll
…
infinite-loop.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
inline-asm.i128.ll
AMDGPU: Add even aligned VGPR/AGPR register classes
2021-02-24 14:49:37 -05:00
inline-asm.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
inline-attr.ll
[funcattrs] Add the maximal set of implied attributes to definitions
2021-04-16 14:22:19 -07:00
inline-calls.ll
…
inline-constraints.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
inline-maxbb.ll
[AMDGPU][Inliner] Remove amdgpu-inline and add a new TTI inline hook
2021-01-21 20:29:17 -08:00
inlineasm-16.ll
…
inlineasm-illegal-type.ll
…
inlineasm-packed.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
input-mods.ll
…
insert-branch-w32.mir
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
insert-skip-from-vcc.mir
[AMDGPU] Translate s_and/s_andn2 to s_mov in vcc optimisation
2020-07-17 11:48:57 +09:00
insert-skips-flat-vmem-ds.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
insert-skips-gws.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
insert-skips-ignored-insts.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
insert-subvector-unused-scratch.ll
[AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
2020-08-21 12:26:31 +02:00
insert-waitcnts-callee.mir
…
insert-waitcnts-exp.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
insert_subreg.ll
…
insert_vector_dynelt.ll
[AMDGPU] Make bfi patterns divergence-aware
2020-09-28 10:16:51 +01:00
insert_vector_elt.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
insert_vector_elt.v2i16.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
insert_vector_elt.v2i16.subtest-saddr.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
inserted-wait-states.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
internalize.ll
[NewPM][AMDGPU] Run InternalizePass when -amdgpu-internalize-symbols
2021-01-04 11:34:40 -08:00
invalid-addrspacecast.ll
…
invariant-load-no-alias-store.ll
…
invert-br-undef-vcc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ipra-regmask.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
ipra.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
jump-address.ll
…
kcache-fold.ll
…
kernarg-size.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
kernarg-stack-alignment.ll
…
kernel-args.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
kernel-argument-dag-lowering.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
kill-infinite-loop.ll
[AMDGPU] Rename SIInsertSkips Pass
2021-03-20 11:48:04 +09:00
known-never-nan.ll
…
known-never-snan.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
knownbits-recursion.ll
…
large-alloca-compute.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
large-alloca-graphics.ll
…
large-constant-initializer.ll
…
large-work-group-promote-alloca.ll
…
lcssa-optnone.ll
…
lds-alignment.ll
[AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering.
2021-06-07 18:00:41 +05:30
lds-bounds.ll
…
lds-branch-vmem-hazard.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
lds-global-non-entry-func.ll
[AMDGPU] Rename "LDS lowering" pass name.
2021-04-14 20:19:53 +05:30
lds-initializer.ll
[Diagnose] Unify MCContext and LLVMContext diagnosing
2021-03-01 15:58:37 -08:00
lds-m0-init-in-loop.ll
…
lds-misaligned-bug.ll
[AMDGPU] Only use ds_read/write_b128 for alignment >= 16
2021-04-08 08:12:05 +05:30
lds-oqap-crash.ll
…
lds-output-queue.ll
…
lds-relocs.ll
[test] Change -t to --syms and -s to -S for llvm-readobj RUN lines
2021-06-29 11:50:31 -07:00
lds-size.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
lds-zero-initializer.ll
[Diagnose] Unify MCContext and LLVMContext diagnosing
2021-03-01 15:58:37 -08:00
lds_atomic_f32.ll
[AMDGPU] Make ds fp atomics overloadable
2020-09-23 11:39:50 -07:00
legalize-fp-load-invariant.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalizedag-bug-expand-setcc.ll
…
limit-coalesce.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
limit-soft-clause-reg-pressure.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
lit.local.cfg
[NFC] Disallow unused prefixes under llvm/test/CodeGen
2021-01-11 12:32:18 -08:00
literals.ll
…
liveness.mir
…
llc-pipeline.ll
[AMDGPU] Move atomic expand past infer address spaces
2021-07-06 15:53:32 -07:00
llvm.amdgcn.alignb.ll
…
llvm.amdgcn.atomic.csub.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
llvm.amdgcn.atomic.dec.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
llvm.amdgcn.atomic.fadd.gfx90a.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.atomic.fadd.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.atomic.inc.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.ballot.i64.ll
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
2020-07-13 12:14:43 +02:00
llvm.amdgcn.buffer.atomic.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.amdgcn.buffer.load.dwordx3.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.buffer.load.format.d16.ll
[AMDGPU] Add v3f16/v3i16 support to SDag
2020-09-16 17:20:27 +02:00
llvm.amdgcn.buffer.load.format.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.buffer.load.ll
[AMDGPU] Use divergent addresses for vector loads
2021-02-23 13:33:15 +00:00
llvm.amdgcn.buffer.store.dwordx3.ll
…
llvm.amdgcn.buffer.store.format.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.buffer.store.format.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.buffer.store.ll
…
llvm.amdgcn.buffer.wbinvl1.ll
…
llvm.amdgcn.buffer.wbinvl1.sc.ll
…
llvm.amdgcn.buffer.wbinvl1.vol.ll
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
2020-06-18 14:12:19 -04:00
llvm.amdgcn.class.f16.ll
…
llvm.amdgcn.class.ll
…
llvm.amdgcn.cos.f16.ll
…
llvm.amdgcn.cos.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubeid.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubema.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubesc.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubetc.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.cvt.pk.i16.ll
…
llvm.amdgcn.cvt.pk.u16.ll
…
llvm.amdgcn.cvt.pknorm.i16.ll
…
llvm.amdgcn.cvt.pknorm.u16.ll
…
llvm.amdgcn.cvt.pkrtz.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.amdgcn.dispatch.id.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
llvm.amdgcn.dispatch.ptr.ll
[amdgpu] Add the late codegen preparation pass.
2020-10-27 14:07:59 -04:00
llvm.amdgcn.div.fixup.f16.ll
…
llvm.amdgcn.div.fixup.ll
…
llvm.amdgcn.div.fmas.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
llvm.amdgcn.div.scale.ll
[AMDGPU] Allow some modifiers on VOP3B instructions
2020-10-28 21:54:14 +00:00
llvm.amdgcn.ds.append.ll
AMDGPU/GlobalISel: Fix not constraining ds_append/consume operands
2020-07-26 10:17:36 -04:00
llvm.amdgcn.ds.bpermute.ll
…
llvm.amdgcn.ds.consume.ll
AMDGPU/GlobalISel: Fix not constraining ds_append/consume operands
2020-07-26 10:17:36 -04:00
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.ds.gws.barrier.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.ds.gws.init.ll
…
llvm.amdgcn.ds.gws.sema.br.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.gws.sema.p.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.gws.sema.release.all.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.ds.gws.sema.v.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.ordered.add.gfx10.ll
…
llvm.amdgcn.ds.ordered.add.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.ds.ordered.swap.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.swizzle.ll
…
llvm.amdgcn.exp.compr.ll
…
llvm.amdgcn.exp.ll
[AMDGPU] Fix scheduling of exp pos4
2020-11-12 19:57:14 +00:00
llvm.amdgcn.exp.prim.ll
…
llvm.amdgcn.fcmp.ll
…
llvm.amdgcn.fdiv.fast.ll
…
llvm.amdgcn.fdot2.ll
…
llvm.amdgcn.fma.legacy.ll
[AMDGPU] Fix test case for D94010
2021-01-19 16:46:47 +00:00
llvm.amdgcn.fmad.ftz.f16.ll
…
llvm.amdgcn.fmad.ftz.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
llvm.amdgcn.fmed3.f16.ll
…
llvm.amdgcn.fmed3.ll
…
llvm.amdgcn.fmul.legacy.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
llvm.amdgcn.fract.f16.ll
…
llvm.amdgcn.fract.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.frexp.exp.f16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
llvm.amdgcn.frexp.exp.ll
…
llvm.amdgcn.frexp.mant.f16.ll
…
llvm.amdgcn.frexp.mant.ll
…
llvm.amdgcn.groupstaticsize.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.groupstaticsize
2020-08-18 09:28:01 -04:00
llvm.amdgcn.icmp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.image.a16.dim.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.a16.encode.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.atomic.dim.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.image.d16.dim.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.image.dim.gfx90a.ll
AMDGPU: Remove special case in shouldCoalesce
2021-02-24 14:49:44 -05:00
llvm.amdgcn.image.dim.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.gather4.o.dim.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.getlod.dim.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.image.load.a16.d16.ll
…
llvm.amdgcn.image.load.a16.ll
…
llvm.amdgcn.image.msaa.load.x.ll
[AMDGPU] Restrict image_msaa_load to MSAA dimension types
2021-03-12 09:47:24 +09:00
llvm.amdgcn.image.nsa.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.sample.a16.dim.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.sample.d16.dim.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.dim.gfx90a.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.image.sample.dim.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.sample.g16.a16.dim.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.sample.g16.encode.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.sample.g16.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.sample.ltolz.ll
…
llvm.amdgcn.image.sample.o.dim.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.store.a16.d16.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.store.a16.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
…
llvm.amdgcn.implicit.buffer.ptr.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.implicitarg.ptr.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
llvm.amdgcn.init.exec.ll
[AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization
2021-01-25 08:31:17 +09:00
llvm.amdgcn.init.exec.wave32.ll
…
llvm.amdgcn.interp.f16.ll
…
llvm.amdgcn.interp.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.intersect_ray.ll
Reland "[AMDGPU] Add gfx1013 target"
2021-06-08 21:15:35 -04:00
llvm.amdgcn.is.private.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.is.shared.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.kernarg.segment.ptr.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
llvm.amdgcn.kill.ll
[AMDGPU] Move kill lowering to WQM pass and add live mask tracking
2021-02-11 20:31:29 +09:00
llvm.amdgcn.ldexp.f16.ll
…
llvm.amdgcn.ldexp.ll
…
llvm.amdgcn.lerp.ll
…
llvm.amdgcn.log.clamp.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.mbcnt.ll
…
llvm.amdgcn.mfma.bf16.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.mfma.gfx90a.ll
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
llvm.amdgcn.mfma.i8.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.mfma.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
2021-02-22 14:59:40 +03:00
llvm.amdgcn.mov.dpp8.ll
…
llvm.amdgcn.mqsad.pk.u16.u8.ll
…
llvm.amdgcn.mqsad.u32.u8.ll
…
llvm.amdgcn.msad.u8.ll
…
llvm.amdgcn.mul.i24.ll
…
llvm.amdgcn.mul.u24.ll
…
llvm.amdgcn.perm.ll
[AMDGPU] Expose __builtin_amdgcn_perm for v_perm_b32
2021-05-06 16:17:33 -07:00
llvm.amdgcn.permlane.ll
…
llvm.amdgcn.ps.live.ll
[AMDGPU] Added -mcpu=tahiti to 3 tests. NFC.
2021-01-25 15:50:59 -08:00
llvm.amdgcn.qsad.pk.u16.u8.ll
…
llvm.amdgcn.queue.ptr.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[AMDGPU] Unify intrinsic ret/nortn interface
2020-09-15 15:26:42 -07:00
llvm.amdgcn.raw.buffer.atomic.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.load.format.d16.ll
[AMDGPU] Add v3f16/v3i16 support to SDag
2020-09-16 17:20:27 +02:00
llvm.amdgcn.raw.buffer.load.format.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.load.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.store.format.ll
…
llvm.amdgcn.raw.buffer.store.ll
…
llvm.amdgcn.raw.tbuffer.load.d16.ll
[AMDGPU] Add v3f16/v3i16 support to SDag
2020-09-16 17:20:27 +02:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions
2021-05-14 10:10:43 +01:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
[AMDGPU] Add v3f16/v3i16 support to SDag
2020-09-16 17:20:27 +02:00
llvm.amdgcn.raw.tbuffer.store.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.rcp.f16.ll
…
llvm.amdgcn.rcp.legacy.ll
…
llvm.amdgcn.rcp.ll
AMDGPU: Remove v_rsq_f64 patterns
2021-01-21 10:51:36 -05:00
llvm.amdgcn.readfirstlane.ll
…
llvm.amdgcn.readlane.ll
…
llvm.amdgcn.rsq.clamp.ll
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
llvm.amdgcn.rsq.f16.ll
…
llvm.amdgcn.rsq.legacy.ll
…
llvm.amdgcn.rsq.ll
…
llvm.amdgcn.s.barrier.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
llvm.amdgcn.s.buffer.load.ll
…
llvm.amdgcn.s.dcache.inv.ll
…
llvm.amdgcn.s.dcache.inv.vol.ll
…
llvm.amdgcn.s.dcache.wb.ll
…
llvm.amdgcn.s.dcache.wb.vol.ll
…
llvm.amdgcn.s.decperflevel.ll
…
llvm.amdgcn.s.get.waveid.in.workgroup.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
llvm.amdgcn.s.getpc.ll
…
llvm.amdgcn.s.getreg.ll
AMDGPU/GlobalISel: Fix selecting llvm.amdgcn.s.getreg
2020-07-28 21:34:50 -04:00
llvm.amdgcn.s.incperflevel.ll
…
llvm.amdgcn.s.memrealtime.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.s.memtime.ll
Revert "Revert "[AMDGPU] Restore the s_memtime instruction in gfx1030""
2021-03-06 09:00:01 +00:00
llvm.amdgcn.s.sethalt.ll
[AMDGPU] New intrinsic void llvm.amdgcn.s.sethalt(i32)
2021-03-01 14:30:23 +00:00
llvm.amdgcn.s.setreg.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.s.waitcnt.ll
…
llvm.amdgcn.sad.hi.u8.ll
…
llvm.amdgcn.sad.u8.ll
…
llvm.amdgcn.sad.u16.ll
…
llvm.amdgcn.sbfe.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.sdot2.ll
…
llvm.amdgcn.sdot4.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
llvm.amdgcn.sdot8.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
llvm.amdgcn.sendmsg.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
llvm.amdgcn.set.inactive.ll
[AMDGPU] Mark V_SET_INACTIVE as defining SCC
2021-01-29 09:46:41 +09:00
llvm.amdgcn.sffbh.ll
…
llvm.amdgcn.sin.f16.ll
…
llvm.amdgcn.sin.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.softwqm.ll
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
2021-03-03 09:33:57 +01:00
llvm.amdgcn.sqrt.f16.ll
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
llvm.amdgcn.sqrt.ll
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
[AMDGPU] Unify intrinsic ret/nortn interface
2020-09-15 15:26:42 -07:00
llvm.amdgcn.struct.buffer.atomic.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.load.format.d16.ll
[AMDGPU] Add v3f16/v3i16 support to SDag
2020-09-16 17:20:27 +02:00
llvm.amdgcn.struct.buffer.load.format.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.load.format.v3f16.ll
[AMDGPU] Fix a crash when selecting a particular case of buffer_load_format_d16
2021-06-03 16:40:18 -04:00
llvm.amdgcn.struct.buffer.load.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.store.format.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.store.format.ll
…
llvm.amdgcn.struct.buffer.store.ll
…
llvm.amdgcn.struct.tbuffer.load.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions
2021-05-14 10:10:43 +01:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.tbuffer.store.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.tbuffer.load.d16.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.load.dwordx3.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.load.ll
[AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions
2021-05-14 10:10:43 +01:00
llvm.amdgcn.tbuffer.store.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.tbuffer.store.dwordx3.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.store.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.trig.preop.ll
…
llvm.amdgcn.ubfe.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
llvm.amdgcn.udot2.ll
[AMDGPU] Added udot2 op_sel test. NFC.
2021-04-09 12:19:42 -07:00
llvm.amdgcn.udot4.ll
…
llvm.amdgcn.udot8.ll
…
llvm.amdgcn.unreachable.ll
…
llvm.amdgcn.update.dpp.ll
[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
2021-02-22 14:59:40 +03:00
llvm.amdgcn.wave.barrier.ll
…
llvm.amdgcn.wavefrontsize.ll
[NewPM][AMDGPU] Pass TargetMachine to AMDGPUSimplifyLibCallsPass
2021-01-04 13:48:09 -08:00
llvm.amdgcn.workgroup.id.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.workitem.id.ll
AMDGPU: Fix checks in llvm.amdgcn.workitem.id.ll
2021-02-18 11:56:15 -05:00
llvm.amdgcn.wqm.demote.ll
[AMDGPU] Fix WQM failure with single block inactive demote
2021-05-06 21:02:26 +09:00
llvm.amdgcn.wqm.vote.ll
[AMDGPU] Move kill lowering to WQM pass and add live mask tracking
2021-02-11 20:31:29 +09:00
llvm.amdgcn.writelane.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.ceil.f16.ll
…
llvm.cos.f16.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
llvm.cos.ll
…
llvm.dbg.value.ll
…
llvm.exp2.f16.ll
…
llvm.exp2.ll
…
llvm.floor.f16.ll
…
llvm.fma.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.fmuladd.f16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.log.f16.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
llvm.log.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.log2.f16.ll
…
llvm.log2.ll
…
llvm.log10.f16.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
llvm.log10.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.maxnum.f16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
llvm.memcpy.ll
…
llvm.minnum.f16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
llvm.mulo.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.pow-gfx9.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
llvm.pow.ll
…
llvm.powi.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
llvm.r600.cube.ll
…
llvm.r600.dot4.ll
…
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
llvm.r600.recipsqrt.clamped.ll
…
llvm.r600.recipsqrt.ieee.ll
…
llvm.r600.tex.ll
…
llvm.rint.f16.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
llvm.rint.f64.ll
…
llvm.rint.ll
…
llvm.round.f64.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
llvm.round.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
llvm.sin.f16.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
llvm.sin.ll
…
llvm.sqrt.f16.ll
…
llvm.trunc.f16.ll
…
lo16-32bit-physreg-copy.mir
…
lo16-hi16-illegal-copy.mir
…
lo16-hi16-physreg-copy.mir
…
lo16-lo16-physreg-copy-agpr.mir
…
lo16-lo16-physreg-copy-sgpr.mir
…
load-constant-f32.ll
…
load-constant-f64.ll
…
load-constant-i1.ll
…
load-constant-i8.ll
…
load-constant-i16.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
load-constant-i32.ll
…
load-constant-i64.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
load-global-f32.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
load-global-f64.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
load-global-i1.ll
…
load-global-i8.ll
…
load-global-i16.ll
[VirtRegRewriter] Insert missing killed flags when tracking subregister liveness
2021-03-03 12:02:04 -05:00
load-global-i32.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
load-global-i64.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
load-hi16.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
load-input-fold.ll
…
load-lo16.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
load-local-f32-no-ds128.ll
…
load-local-f32.ll
[AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
2020-08-21 12:26:31 +02:00
load-local-f64.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
load-local-i1.ll
…
load-local-i8.ll
[AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
2020-08-21 12:26:31 +02:00
load-local-i16.ll
[AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
2020-08-21 12:26:31 +02:00
load-local-i32.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
load-local-i64.ll
…
load-local-redundant-copies.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
load-local.96.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
load-local.128.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
load-select-ptr.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
load-store-opt-scc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
load-weird-sizes.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
local-64.ll
…
local-atomics-fp.ll
[AMDGPU] Limit memory scope for scratch, LDS and GDS
2021-02-14 17:34:12 +00:00
local-atomics.ll
…
local-atomics64.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
local-memory.amdgcn.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
local-memory.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
local-memory.r600.ll
…
local-stack-alloc-block-sp-reference.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
local-stack-slot-offset.ll
…
loop-address.ll
…
loop-idiom.ll
[BasicAA] Rename deprecated -basicaa to -basic-aa
2020-06-26 20:41:37 -07:00
loop-live-out-copy-undef-subrange.ll
RegisterCoalescer: Prune undef subranges from copy pairs in loops
2021-02-03 13:42:53 -05:00
loop-prefetch.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
loop_break.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
loop_exit_with_xor.ll
[AMDGPU] Move code sinking before structurizer
2021-05-11 14:07:23 +02:00
loop_header_nopred.mir
[AMDGPU] Remove SI_MASK_BRANCH
2021-03-09 09:13:23 +08:00
lower-control-flow-other-terminators.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
lower-kernargs.ll
Use unary CreateShuffleVector if possible
2020-12-30 22:36:08 +09:00
lower-kernel-and-module-lds.ll
[AMDGPU] Propagate LDS align into to instructions
2021-06-23 00:57:16 -07:00
lower-kernel-lds-constexpr.ll
[AMDGPU] Propagate LDS align into to instructions
2021-06-23 00:57:16 -07:00
lower-kernel-lds-global-uses.ll
[AMDGPU] Propagate LDS align into to instructions
2021-06-23 00:57:16 -07:00
lower-kernel-lds-super-align.ll
[AMDGPU] Check for pointer operand while refining LDS align
2021-06-23 12:27:55 -07:00
lower-kernel-lds.ll
[AMDGPU] Propagate LDS align into to instructions
2021-06-23 00:57:16 -07:00
lower-mem-intrinsics-threshold.ll
…
lower-mem-intrinsics.ll
…
lower-module-lds-constantexpr.ll
[AMDGPU] Use performOptimizedStructLayout for LDS sort
2021-06-22 09:58:10 -07:00
lower-module-lds-global-alias.ll
[AMDGPU] Use performOptimizedStructLayout for LDS sort
2021-06-22 09:58:10 -07:00
lower-module-lds-global-uses.ll
[AMDGPU] Use performOptimizedStructLayout for LDS sort
2021-06-22 09:58:10 -07:00
lower-module-lds-inactive.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
lower-module-lds-indirect.ll
[AMDGPU] Fix module LDS selection
2021-05-20 15:59:01 -07:00
lower-module-lds-offsets.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
lower-module-lds-used-list.ll
[AMDGPU] Propagate LDS align into to instructions
2021-06-23 00:57:16 -07:00
lower-module-lds.ll
[AMDGPU] Propagate LDS align into to instructions
2021-06-23 00:57:16 -07:00
lower-range-metadata-intrinsic-call.ll
…
lower-term-opcodes.mir
[AMDGPU] Fix lowering of S_MOV_{B32,B64}_term
2020-11-10 12:16:31 +09:00
lshl64-to-32.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
lshr.v2i16.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
machine-cse-commute-target-flags.mir
AMDGPU: Support commuting register and global operand
2020-07-01 13:59:13 -04:00
machinelicm-convergent.mir
Prevent LICM and machineLICM from hoisting convergent operations
2020-11-06 10:26:39 -08:00
macro-fusion-cluster-vcc-uses.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
mad-combine.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
mad-mix-hi.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
mad-mix-lo.ll
AMDGPU: Add missing tests for v_fma_mixlo
2021-06-21 10:58:53 -04:00
mad-mix.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
mad.u16.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
mad24-get-global-id.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
mad_64_32.ll
…
mad_int24.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
mad_uint24.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
madak-inline-constant.mir
…
madak.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
madmk.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
mai-hazards-gfx90a.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
mai-hazards.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
mai-inline.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
max-literals.ll
…
max-sgprs.ll
…
max.i16.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
max.ll
…
max3.ll
…
mcp-overlap-after-propagation.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
med3-no-simplify.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
mem-builtins.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
memcpy-fixed-align.ll
[AMDGPU] Enable multi-dword flat scratch load/stores
2020-11-12 13:38:56 -08:00
memcpy-inline-fails.ll
…
memcpy-scoped-aa.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
memory-legalizer-atomic-insert-end.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
memory-legalizer-fence.ll
[AMDGPU] Update gfx90a memory model support
2021-06-30 04:05:22 +00:00
memory-legalizer-flat-agent.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
memory-legalizer-flat-nontemporal.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
memory-legalizer-flat-singlethread.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-flat-system.ll
[AMDGPU] Update gfx90a memory model support
2021-06-30 04:05:22 +00:00
memory-legalizer-flat-volatile.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
memory-legalizer-flat-wavefront.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-flat-workgroup.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
memory-legalizer-global-agent.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
memory-legalizer-global-nontemporal.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-global-singlethread.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
memory-legalizer-global-system.ll
[AMDGPU] Update gfx90a memory model support
2021-06-30 04:05:22 +00:00
memory-legalizer-global-volatile.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
memory-legalizer-global-wavefront.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
memory-legalizer-global-workgroup.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
memory-legalizer-invalid-addrspace.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
memory-legalizer-invalid-syncscope.ll
…
memory-legalizer-local-agent.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local-nontemporal.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local-singlethread.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local-system.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local-volatile.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
memory-legalizer-local-wavefront.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local-workgroup.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
memory-legalizer-multiple-mem-operands-atomics.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
memory-legalizer-private-nontemporal.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-private-volatile.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
memory-legalizer-region.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
memory-legalizer-store-infinite-loop.ll
…
memory_clause.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
memory_clause.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-image-load-gfx10.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-image-load.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-image-sample-gfx10.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-image-sample.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-load-store-agpr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-load-store-physreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-load-store-vreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-load-store.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-m0.mir
[AMDGPU] Remove gds operand from ds_gws_* MachineInstrs
2020-10-29 15:04:23 +00:00
merge-out-of-order-ldst.ll
…
merge-out-of-order-ldst.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-store-crash.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
merge-store-usedef.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
merge-stores.ll
[AMDGPU] Add alignment check for v3 to v4 load type promotion
2020-11-01 12:05:34 +05:30
merge-tbuffer.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
mesa3d.ll
…
mesa_regression.ll
…
mfma-loop.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
min.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
min3.ll
…
mir-print-dead-csr-fi.mir
…
misched-killflags.mir
…
missing-store.ll
…
mixed-wave32-wave64.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
mixed_wave32_wave64.ll
…
mode-register.mir
[AMDGPU] Avoid redundant mode register writes
2020-06-24 14:11:29 +01:00
move-addr64-rsrc-dead-subreg-writes.ll
…
move-load-addr-to-valu.mir
[AMDGPU] Change FLAT Scratch SADDR to VADDR form in moveToVALU
2021-05-03 10:57:14 -07:00
move-to-valu-atomicrmw.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
move-to-valu-worklist.ll
…
movreld-bug.ll
[AMDGPU] Make movreld-bug test case more robust
2020-09-11 10:25:29 +01:00
movrels-bug.mir
…
mubuf-legalize-operands.ll
[AMDGPU] Don't check for VMEM hazards on GFX10
2021-03-04 21:44:56 +00:00
mubuf-legalize-operands.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
mubuf-offset-private.ll
…
mubuf-shader-vgpr.ll
…
mubuf.ll
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
mul.i16.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
mul.ll
…
mul24-pass-ordering.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
mul_int24.ll
[AMDGPU] Stop mulhi from doing 24 bit mul for uniform values
2021-07-05 10:33:23 +01:00
mul_uint24-amdgcn.ll
[AMDGPU] Stop mulhi from doing 24 bit mul for uniform values
2021-07-05 10:33:23 +01:00
mul_uint24-r600.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
multi-divergent-exit-region.ll
[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree
2021-01-02 01:01:20 +03:00
multi-dword-vgpr-spill.ll
[AMDGPU] Use multi-dword flat scratch for spilling
2020-12-14 14:19:29 -08:00
multilevel-break.ll
[AMDGPU] Move code sinking before structurizer
2021-05-11 14:07:23 +02:00
nand.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
need-fp-from-csr-vgpr-spill.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
nested-calls.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
nested-loop-conditions.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
no-bundle-asm.ll
AMDGPU: Do not bundle inline asm
2020-06-14 13:24:50 -04:00
no-hsa-graphics-shaders.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
no-initializer-constant-addrspace.ll
[llvm-readobj] - For SHT_REL relocations, don't display an addend.
2020-12-14 12:03:00 +03:00
no-remat-indirect-mov.mir
…
no-shrink-extloads.ll
…
non-entry-alloca.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
noop-shader-O0.ll
…
nop-data.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
nor.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
not-scalarize-volatile-load.ll
…
nsa-reassign.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
nsa-reassign.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
nsa-vmem-hazard.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
nullptr.ll
…
occupancy-levels.ll
[AMDGPU] Add occupancy level tests for GFX10.3. NFC.
2020-12-08 14:15:01 +00:00
offset-split-flat.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
offset-split-global.ll
[AMDGPU] Improve global SADDR selection
2021-05-05 14:44:21 -07:00
omod-nsz-flag.mir
…
omod.ll
[AMDGPU] Enable output modifiers for double precision instructions
2021-04-01 10:08:17 -04:00
opencl-image-metadata.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
opencl-printf-no-hostcall.ll
…
opencl-printf.ll
[NewPM][AMDGPU] Port amdgpu-printf-runtime-binding
2021-01-04 12:25:50 -08:00
operand-folding.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
operand-spacing.ll
…
opt-pipeline.ll
Revert "[AMDGPU] [IndirectCalls] Don't propagate attributes to address taken functions and their callees"
2021-06-24 02:33:50 +01:00
opt-sgpr-to-vgpr-copy.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
opt_exec_copy_fold.mir
[AMDGPU] SIOptimizeExecMaskingPreRA should check constant bus constraint when folds EXEC copy
2021-03-24 14:14:13 +03:00
optimize-exec-copies-extra-insts-after-copy.mir
AMDGPU: Optimize copies to exec with other insts after exec def
2020-07-28 21:34:50 -04:00
optimize-exec-mask-pre-ra-loop-phi.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
optimize-exec-masking-pre-ra.mir
[AMDGPU] Remove SI_MASK_BRANCH
2021-03-09 09:13:23 +08:00
optimize-exec-masking-strip-terminator-bits.mir
AMDGPU: Don't assume there is only one terminator copy
2020-07-28 20:22:38 -04:00
optimize-if-exec-masking.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
optimize-negated-cond-exec-masking-wave32.mir
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
optimize-negated-cond-exec-masking.mir
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
optimize-negated-cond.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
or.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
or3.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
pack.v2f16.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
pack.v2i16.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
packed-fp32.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
packed-op-sel.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
packetizer.ll
…
pal-simple-indirect-call.ll
[AMDGPU][GlobalISel] Allow amdgpu_gfx calling conv
2021-05-27 10:41:40 +02:00
pal-userdata-regs.ll
…
parallelandifcollapse.ll
…
parallelorifcollapse.ll
…
partial-sgpr-to-vgpr-spills.ll
[AMDGPU] Save VGPR of whole wave when spilling
2021-04-12 11:01:38 +02:00
partial-shift-shrink.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
partially-dead-super-register-immediate.ll
…
peephole-opt-regseq-removal.mir
…
pei-build-spill-partial-agpr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pei-build-spill.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pei-reg-scavenger-position.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pei-scavenge-sgpr-carry-out.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pei-scavenge-sgpr-gfx9.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pei-scavenge-sgpr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pei-scavenge-vgpr-spill.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
perfhint.ll
[AMDGPU] Add some missing check prefixes and tweak test
2020-07-17 12:57:47 +01:00
permute.ll
…
phi-elimination-assertion.mir
…
phi-elimination-end-cf.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
phi-vgpr-input-moveimm.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
pk_max_f16_literal.ll
…
post-ra-sched-kill-bundle-use-inst.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
post-ra-sched-reset.mir
[AMDGPU] Add Reset function to GCNHazardRecognizer
2020-10-28 16:32:32 -07:00
post-ra-soft-clause-dbg-info.ll
AMDGPU: Fix debug info handling in post-RA bundler
2021-02-16 10:42:06 -05:00
postra-bundle-memops.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postra-machine-sink.mir
…
postra-norename.mir
…
power-sched-no-instr-sunit.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
predicate-dp4.ll
…
predicates.ll
…
preserve-hi16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
print-mir-custom-pseudo.ll
[AMDGPU] Implement mir parseCustomPseudoSourceValue
2021-01-22 11:24:08 +01:00
private-access-no-objects.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
private-element-size.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
private-memory-atomics.ll
…
private-memory-r600.ll
[AMDGPU, test] Fix use of undef FileCheck var
2021-04-08 09:42:59 +01:00
promote-alloca-addrspacecast.ll
…
promote-alloca-array-aggregate.ll
…
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
…
promote-alloca-calling-conv.ll
…
promote-alloca-globals.ll
[AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering.
2021-06-07 18:00:41 +05:30
promote-alloca-invariant-markers.ll
…
promote-alloca-lifetime.ll
…
promote-alloca-mem-intrinsics.ll
[AMDGPU] Fix promote alloca with double use in a same insn
2021-02-11 11:42:25 -08:00
promote-alloca-no-opts.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
promote-alloca-padding-size-estimate.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
promote-alloca-pointer-array.ll
…
promote-alloca-stored-pointer-value.ll
…
promote-alloca-to-lds-constantexpr-use.ll
[AMDGPU] Rename "LDS lowering" pass name.
2021-04-14 20:19:53 +05:30
promote-alloca-to-lds-icmp.ll
…
promote-alloca-to-lds-phi.ll
[NFC] GetUnderlyingObject -> getUnderlyingObject
2020-07-30 21:08:24 -07:00
promote-alloca-to-lds-select.ll
[ValueTracking, BasicAA] Don't simplify instructions
2020-06-21 16:31:07 +02:00
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-vector-to-vector.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
promote-alloca-volatile.ll
…
promote-constOffset-to-imm-gfx10.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
promote-constOffset-to-imm-gfx90a.mir
AMDGPU: Fix SILoadStoreOptimizer for gfx90a
2021-05-11 21:26:43 -04:00
promote-constOffset-to-imm.ll
AMDGPU: Fix SILoadStoreOptimizer for gfx90a
2021-05-11 21:26:43 -04:00
promote-constOffset-to-imm.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
promote-vect3-load.ll
[AMDGPU] Add alignment check for v3 to v4 load type promotion
2020-11-01 12:05:34 +05:30
propagate-attributes-bitcast-function.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
propagate-attributes-clone.ll
[NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late
2021-01-04 11:53:37 -08:00
propagate-attributes-flat-work-group-size.ll
[NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late
2021-01-04 11:53:37 -08:00
propagate-attributes-function-pointer-argument.ll
Revert "[AMDGPU] [IndirectCalls] Don't propagate attributes to address taken functions and their callees"
2021-06-24 02:33:50 +01:00
propagate-attributes-single-set.ll
[NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late
2021-01-04 11:53:37 -08:00
ptr-arg-dbg-value.ll
[LiveDebugVariables] Stop trimming locations of non-inlined vars
2021-05-31 02:59:19 -07:00
ptrmask.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
pv-packing.ll
…
pv.ll
…
r600-constant-array-fixup.ll
[llvm-readobj] - For SHT_REL relocations, don't display an addend.
2020-12-14 12:03:00 +03:00
r600-encoding.ll
…
r600-export-fix.ll
…
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600-legalize-umax-bug.ll
[DAG] SimplifyDemandedBits - use KnownBits comparisons to remove ISD::UMIN/UMAX ops
2021-01-18 10:29:23 +00:00
r600.add.ll
…
r600.alu-limits.ll
…
r600.amdgpu-alias-analysis.ll
…
r600.bitcast.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
r600.extract-lowbits.ll
…
r600.func-alignment.ll
…
r600.global_atomics.ll
…
r600.private-memory.ll
…
r600.sub.ll
…
r600.work-item-intrinsics.ll
…
r600cfg.ll
…
rcp-pattern.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
rcp_iflag.ll
…
read-register-invalid-subtarget.ll
…
read-register-invalid-type-i32.ll
…
read-register-invalid-type-i64.ll
…
read_register.ll
…
readcyclecounter.ll
[AMDGPU] Add some GFX10.3 testing. NFC.
2021-05-11 11:21:19 +01:00
readlane_exec0.mir
[AMDGPU] Rename SIInsertSkips Pass
2021-03-20 11:48:04 +09:00
reassoc-scalar.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
reduce-build-vec-ext-to-ext-build-vec.ll
…
reduce-load-width-alignment.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
reduce-saveexec.mir
…
reduce-store-width-alignment.ll
…
reduction.ll
…
reg-coalescer-sched-crash.ll
…
regcoal-subrange-join-seg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regcoal-subrange-join.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
regcoalesce-cannot-join-failures.mir
…
regcoalesce-dbg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
…
regcoalesce-prune.mir
…
regcoalescing-remove-partial-redundancy-assert.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
register-count-comments.ll
…
rel32.ll
[AMDGPU] Add some gfx1010 test coverage. NFC.
2021-03-18 14:00:07 +00:00
remat-fp64-constants.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
remove-short-exec-branches-gpr-idx-mode.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
remove-short-exec-branches-special-instructions.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
rename-disconnected-bug.ll
…
rename-independent-subregs-mac-operands.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
rename-independent-subregs.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
reorder-stores.ll
…
replace-lds-by-ptr-call-diamond-shape.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-call-selected_functions.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-ignore-global-scope-use.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-ignore-inline-asm-call.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-ignore-kernel-only-used-lds.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-ignore-not-reachable-lds.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-ignore-small-lds.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-indirect-call-diamond-shape.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-indirect-call-selected_functions.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-indirect-call-signature-match.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-use-multiple-lds.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-use-same-lds.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-use-within-const-expr1.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-use-within-const-expr2.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
replace-lds-by-ptr-use-within-phi-inst.ll
Disable ReplaceLDS pass, patch up tests to match
2021-06-26 01:36:42 +01:00
reqd-work-group-size.ll
[NewPM][AMDGPU] Port amdgpu-lower-kernel-attributes
2020-12-29 10:26:06 -08:00
reserve-vgpr-for-sgpr-spill.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
reserved-reg-in-clause.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
ret.ll
…
ret_jump.ll
[AMDGPU] Keep skip branch for ds instructions
2021-03-05 12:34:09 +01:00
return-with-successors.mir
AMDGPU: Implement getNoPreservedMask
2020-10-22 10:17:31 -04:00
returnaddress.ll
AMDGPU/GlobalISel: Select llvm.returnaddress
2020-08-04 17:14:38 -04:00
rewrite-out-arguments-address-space.ll
Use unary CreateShuffleVector if possible
2020-12-30 22:36:08 +09:00
rewrite-out-arguments.ll
Use unary CreateShuffleVector if possible
2020-12-30 22:36:08 +09:00
rotl.i64.ll
…
rotl.ll
[AMDGPU] should expand ROTL i16 to shifts.
2020-09-17 17:34:33 +03:00
rotr.i64.ll
…
rotr.ll
[AMDGPU] should expand ROTL i16 to shifts.
2020-09-17 17:34:33 +03:00
rsq.ll
AMDGPU: Remove v_rsq_f64 patterns
2021-01-21 10:51:36 -05:00
rv7x0_count3.ll
…
s_add_co_pseudo_lowering.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
s_addk_i32.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
s_code_end.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
s_movk_i32.ll
…
s_mulk_i32.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
sad.ll
[EarlyCSE] Remove unnecessary operand swap.
2020-09-11 02:14:04 -04:00
saddo.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
saddsat.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
salu-to-valu.ll
[AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions
2021-05-14 10:10:43 +01:00
sampler-resource-id.ll
…
scalar-branch-missing-and-exec.ll
…
scalar-store-cache-flush.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
scalar_to_vector.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
scalar_to_vector_v2x16.ll
…
sched-assert-dead-def-subreg-use-other-subreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sched-assert-onlydbg-value-empty-region.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sched-crash-dbg-value.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sched-handleMoveUp-subreg-def-across-subreg-def.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sched-prefer-non-mfma.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
schedule-barrier-fpmode.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
schedule-barrier.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
schedule-fs-loop-nested-if.ll
…
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-ilp.ll
…
schedule-kernel-arg-loads.ll
…
schedule-regpressure-limit-clustering.ll
[AMDGPU] Fix not rescheduling without clustering
2020-08-07 11:15:58 -07:00
schedule-regpressure-limit.ll
[amdgpu] Enable use of AA during codegen.
2020-10-27 09:46:23 -04:00
schedule-regpressure-limit2.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
schedule-regpressure-limit3.ll
[amdgpu] Enable use of AA during codegen.
2020-10-27 09:46:23 -04:00
schedule-regpressure.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
schedule-vs-if-nested-loop-failure.ll
…
schedule-vs-if-nested-loop.ll
…
schedule-xdl-resource.ll
[AMDGPU] Add XDL resource to scheduling model
2020-09-14 13:48:54 -07:00
scheduler-handle-move-bundle.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
scheduler-subrange-crash.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
scratch-buffer.ll
…
scratch-simple.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
sdiv.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
sdiv64.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
sdivrem24.ll
…
sdivrem64.r600.ll
…
sdwa-gfx9.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sdwa-op64-test.ll
AMDGPU: Match global saddr addressing mode
2020-08-17 15:28:14 -04:00
sdwa-ops.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sdwa-peephole-instr-gfx10.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sdwa-peephole-instr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sdwa-peephole.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
sdwa-preserve.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sdwa-scalar-ops.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sdwa-stack.mir
[AMDGPU] Inhibit SDWA if target instruction has FI
2020-08-13 11:34:28 -07:00
sdwa-vop2-64bit.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-constant-cttz.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
select-fabs-fneg-extract-legacy.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
select-fabs-fneg-extract.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
select-i1.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
select-opt.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
select-undef.ll
…
select-vectors.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
select.f16.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
select.ll
…
select64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll
…
selectcc-opt.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
selectcc.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
sendmsg-m0-hazard.mir
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
set-dx10.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
set-gpr-idx-peephole.mir
[AMDGPU] Remove set_gpr_idx instructions in conditional blocks
2021-04-30 22:15:45 +01:00
setcc-equivalent.ll
…
setcc-fneg-constant.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
setcc-limit-load-shrink.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
setcc-opt.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
setcc-sext.ll
…
setcc.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
setcc64.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
seto.ll
…
setuo.ll
…
sext-divergence-driven-isel.ll
…
sext-eliminate.ll
…
sext-in-reg-failure-r600.ll
…
sext-in-reg.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
sgpr-control-flow.ll
[AMDGPU] Add Optimize VGPR LiveRange Pass.
2021-06-21 15:25:55 +08:00
sgpr-copy-duplicate-operand.ll
…
sgpr-copy-local-cse.ll
[PeepholeOptimizer] Enhance the redundant COPY elimination.
2020-09-22 10:11:37 -04:00
sgpr-copy.ll
…
sgpr-phys-copy.mir
[AMDGPU] Minimize number of s_mov generated by copyPhysReg
2020-10-15 22:35:02 +09:00
sgpr-spill-dead-frame-in-dbg-value.mir
[AMDGPU] Fix the dead frame indices during custom spill lowering.
2021-03-09 23:22:49 +05:30
sgpr-spill-partially-undef.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sgpr-spill-wrong-stack-id.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sgpr-spill.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sgprcopies.ll
…
shader-addr64-nonuniform.ll
…
shared-op-cycle.ll
…
shift-and-i64-ubfe.ll
…
shift-and-i128-ubfe.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
shift-i64-opts.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
shift-i128.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
shift-select.ll
…
shl-add-to-add-shl.ll
…
shl.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
shl.v2i16.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
shl_add.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
shl_add_constant.ll
…
shl_add_ptr.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
shl_add_ptr_csub.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
shl_add_ptr_global.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
shl_or.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
shrink-add-sub-constant.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
shrink-carry.mir
[AMDGPU] Rename SIInsertSkips Pass
2021-03-20 11:48:04 +09:00
shrink-instructions-flags.mir
…
shrink-instructions-illegal-fold.mir
[AMDGPU] Avoid an illegal operand in si-shrink-instructions
2021-01-28 08:49:21 +01:00
shrink-instructions-implicit-vcclo.mir
[AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK
2020-08-27 10:22:50 +02:00
shrink-insts-scalar-bit-ops.mir
AMDGPU: Fix verifier error with undef source producing s_bitset*
2020-08-05 14:42:20 -04:00
shrink-vop3-carry-out.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
si-annotate-cf-kill.ll
[AMDGPU] Do not annotate an else branch if there is a kill
2021-03-12 11:52:08 +09:00
si-annotate-cf-noloop.ll
[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree
2021-01-02 01:01:20 +03:00
si-annotate-cf-unreachable.ll
…
si-annotate-cf.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
si-annotate-cfg-loop-assert.ll
[AMDGPU] Fix and extend vccz workarounds
2020-11-18 15:26:06 +00:00
si-annotatecfg-multiple-backedges.ll
…
si-fix-sgpr-copies.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
si-i1-copies.mir
…
si-instr-info-correct-implicit-operands.ll
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
si-lower-control-flow-kill.ll
…
si-lower-control-flow-unreachable-block.ll
[AMDGPU] Keep skip branch for ds instructions
2021-03-05 12:34:09 +01:00
si-lower-control-flow.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
si-lower-i1-copies.mir
…
si-lower-sgpr-spills.mir
…
si-scheduler.ll
[AMDGPU] Added -mcpu=tahiti to 3 tests. NFC.
2021-01-25 15:50:59 -08:00
si-sgpr-spill.ll
[AMDGPU] Added -mcpu=tahiti to 3 tests. NFC.
2021-01-25 15:50:59 -08:00
si-spill-cf.ll
…
si-spill-sgpr-stack.ll
[AMDGPU] Save VGPR of whole wave when spilling
2021-04-12 11:01:38 +02:00
si-triv-disjoint-mem-access.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
si-vector-hang.ll
…
sibling-call.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
sign_extend.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
simple-indirect-call.ll
[AMDGPU] Remove error check for indirect calls and add missing queue-ptr
2021-04-20 00:35:17 +05:30
simplify-libcalls.ll
[amdgpu] Add `-enable-ocl-mangling-mismatch-workaround`.
2021-06-08 15:42:27 -04:00
simplify-libcalls2.ll
[NewPM][AMDGPU] Port amdgpu-simplifylib/amdgpu-usenative
2020-12-28 10:38:51 -08:00
simplifydemandedbits-recursion.ll
…
sink-image-sample.ll
[AMDGPU] Move code sinking before structurizer
2021-05-11 14:07:23 +02:00
sint_to_fp.f64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
sint_to_fp.i64.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
sint_to_fp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
sitofp.f16.ll
…
skip-branch-taildup-ret.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
skip-branch-trap.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
skip-if-dead.ll
[AMDGPU] Add Optimize VGPR LiveRange Pass.
2021-06-21 15:25:55 +08:00
skip-promote-alloca-vector-users.ll
[AMDGPU] Skip promote-alloca for insertelement/insertvalue users
2021-04-30 08:37:26 +05:30
smed3.ll
[amdgpu] Update med3 combine to skip i64
2021-03-18 15:56:41 +00:00
smem-no-clause-coalesced.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
smem-war-hazard.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sminmax.ll
…
sminmax.v2i16.ll
…
smrd-fold-offset.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
smrd-gfx10.ll
…
smrd-vccz-bug.ll
…
smrd.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
smrd_vmem_war.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
soft-clause-dbg-value.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
soft-clause-exceeds-register-budget.ll
[AMDGPU] Switch AnnotateUniformValues to MemorySSA
2021-05-05 18:34:41 -07:00
sopk-compares.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
speculative-execution-freecasts.ll
…
spill-agpr-partially-undef.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
spill-agpr.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
spill-agpr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
spill-alloc-sgpr-init-bug.ll
…
spill-before-exec.mir
[AMDGPU] Remove weird target triples from tests. NFC.
2021-03-19 16:48:32 +00:00
spill-cfg-position.ll
…
spill-csr-frame-ptr-reg-copy.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
spill-empty-live-interval.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
spill-m0.ll
[AMDGPU] Save VGPR of whole wave when spilling
2021-04-12 11:01:38 +02:00
spill-offset-calculation.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
spill-reg-tuple-super-reg-use.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
spill-scavenge-offset.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
spill-sgpr-csr-live-ins.mir
AMDGPU: Fix verifier error with argument passed in CSR SGPR
2021-02-09 13:49:44 -05:00
spill-sgpr-stack-no-sgpr.ll
[AMDGPU] Save VGPR of whole wave when spilling
2021-04-12 11:01:38 +02:00
spill-special-sgpr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
spill-vgpr-to-agpr.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
spill-wide-sgpr.ll
[NFC][AMDGPU] Clean up some lit test prefixes
2020-11-11 17:12:37 +00:00
spill192.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
spill224.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
spill_more_than_wavesize_csr_sgprs.ll
[AMDGPU] Use pseudo instructions for readlane/writelane
2020-10-29 16:00:53 +00:00
split-arg-dbg-value.ll
[MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling
2021-05-06 04:53:45 +05:30
split-scalar-i64-add.ll
…
split-smrd.ll
…
split-vector-memoperand-offsets.ll
…
splitkit-copy-bundle.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
splitkit-copy-live-lanes.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
splitkit-getsubrangeformask.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
splitkit-nolivesubranges.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
splitkit.mir
[VirtRegRewriter] Insert missing killed flags when tracking subregister liveness
2021-03-03 12:02:04 -05:00
sra.ll
[DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts
2021-05-07 13:12:30 +01:00
sram-ecc-default.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
sramecc-subtarget-feature-any.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
sramecc-subtarget-feature-disabled.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
sramecc-subtarget-feature-enabled.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
srem-seteq-illegal-types.ll
Support {S,U}REMEqFold before legalization
2021-04-01 01:35:41 +03:00
srem.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
srem64.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
srl.ll
[DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts
2021-05-07 13:12:30 +01:00
sroa-before-unroll.ll
[AMDGPU][NewPM] Port amdgpu-promote-alloca(-to-vector)
2020-12-28 17:52:31 -08:00
ssubo.ll
…
ssubsat.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
stack-pointer-offset-relative-frameindex.ll
[AMDGPU] Don't check for VMEM hazards on GFX10
2021-03-04 21:44:56 +00:00
stack-realign-kernel.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
stack-realign.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
stack-size-overflow.ll
Improve the diagnostic of DiagnosticInfoResourceLimit (and warn-stack-size in particular)
2021-06-22 09:55:20 -07:00
stack-slot-color-sgpr-vgpr-spills.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
stale-livevar-in-twoaddr-pass.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
store-barrier.ll
…
store-clobbers-load.ll
AMDGPU: Annotate amdgpu.noclobber for global loads only
2021-01-05 14:47:19 -08:00
store-global.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
store-hi16.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
store-local.96.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
store-local.128.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
store-local.ll
[AMDGPU] Set DS alignment requirements to be more strict
2020-09-18 15:26:24 +02:00
store-private.ll
…
store-v3i64.ll
…
store-vector-ptrs.ll
…
store-weird-sizes.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
store_typed.ll
…
stress-calls.ll
…
strict_fadd.f16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
strict_fadd.f32.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fadd.f64.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
strict_fma.f16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
strict_fma.f32.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fma.f64.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
strict_fmul.f16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
strict_fmul.f32.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fmul.f64.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
strict_fsub.f16.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
strict_fsub.f32.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fsub.f64.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
structurize.ll
…
structurize1.ll
…
sub-zext-cc-zext-cc.ll
…
sub.i16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
sub.ll
…
sub.v2i16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
sub_i1.ll
…
subreg-coalescer-crash.ll
…
subreg-coalescer-undef-use.ll
…
subreg-eliminate-dead.ll
…
subreg-intervals.mir
…
subreg-split-live-in-error.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
subreg-undef-def-with-other-subreg-defs.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
subreg_interference.mir
[VirtRegRewriter] Insert missing killed flags when tracking subregister liveness
2021-03-03 12:02:04 -05:00
subvector-test.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
swdev282079.ll
AMDGPU: Fix assert on inline asm on gfx90a
2021-04-23 09:00:25 -04:00
swdev282079.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
switch-default-block-unreachable.ll
[AMDGPU] Move LowerSwitch pass to CodeGenPrepare.
2020-07-11 16:33:38 +05:30
switch-unreachable.ll
…
swizzle-export.ll
…
syncscopes.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
tail-call-amdgpu-gfx.ll
[TargetLowering] Only inspect attributes in the arguments for ArgListEntry
2021-05-18 14:30:22 -07:00
tail-call-cgp.ll
…
tail-dup-bundle.mir
…
tail-duplication-convergent.ll
…
target-cpu.ll
…
tex-clause-antidep.ll
…
texture-input-merge.ll
…
tgsplit.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
tid-code-object-v2-backwards-compatibility.ll
AMDGPU: Add gfx90c support to code object v2 for backwards compatibility
2021-04-08 16:42:43 -04:00
tid-mul-func-xnack-all-any.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-not-supported.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-off.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-on.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-off-1.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-off-2.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-on-1.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-on-2.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-invalid-any-off-on.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-one-func-xnack-any.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-one-func-xnack-not-supported.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-one-func-xnack-off.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-one-func-xnack-on.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
token-factor-inline-limit-test.ll
[AMDGPU] Don't cluster stores
2020-09-14 13:40:17 +01:00
transform-block-with-return-to-epilog.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
trap-abis.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
trap.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
trunc-bitcast-vector.ll
…
trunc-cmp-constant.ll
…
trunc-combine.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
trunc-store-f64-to-f16.ll
…
trunc-store-i1.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-07 09:48:14 -08:00
trunc-store-i64.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
trunc-store-vec-i16-to-i8.ll
…
trunc-store.ll
…
trunc-vector-store-assertion-failure.ll
…
trunc.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
tti-unroll-prefs.ll
…
twoaddr-fma-f64.mir
AMDGPU: Add even aligned VGPR/AGPR register classes
2021-02-24 14:49:37 -05:00
twoaddr-fma.mir
…
twoaddr-mad.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
uaddo.ll
…
uaddsat.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
udiv.ll
[DAGCombiner] Add support for mulhi const folding in DAGCombiner
2021-07-05 12:01:26 +01:00
udiv64.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
udivrem.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
udivrem24.ll
…
udivrem64.r600.ll
…
uint_to_fp.f64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
uint_to_fp.i64.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-07 09:48:14 -08:00
uint_to_fp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
uitofp.f16.ll
…
umed3.ll
…
unaligned-load-store.ll
[AMDGPU] Support unaligned flat scratch in TLI
2020-12-22 16:12:31 -08:00
unallocatable-bundle-regression.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
undef-subreg-use-after-coalesce.mir
RegisterCoalescer: Fix not setting undef on coalesced subregister uses
2021-02-03 13:54:43 -05:00
undefined-physreg-sgpr-spill.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
undefined-subreg-liverange.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
unexpected-reg-unit-state.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
unhandled-loop-condition-assertion.ll
…
uniform-branch-intrinsic-cond.ll
…
uniform-cfg.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
uniform-crash.ll
…
uniform-loop-inside-nonuniform.ll
…
uniform-work-group-attribute-missing.ll
…
uniform-work-group-nested-function-calls.ll
…
uniform-work-group-prevent-attribute-propagation.ll
…
uniform-work-group-propagate-attribute.ll
…
uniform-work-group-recursion-test.ll
…
uniform-work-group-test.ll
…
unify-metadata.ll
[NewPM][AMDGPU] Port amdgpu-unify-metadata
2021-01-04 11:57:46 -08:00
unigine-liveness-crash.ll
[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree
2021-01-02 01:01:20 +03:00
unknown-processor.ll
…
unpack-half.ll
…
unroll.ll
[AMDGPU][CostModel] Refine cost model for control-flow instructions.
2021-04-10 09:20:24 +03:00
unstructured-cfg-def-use-issue.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
unsupported-calls.ll
[AMDGPU] Remove error check for indirect calls and add missing queue-ptr
2021-04-20 00:35:17 +05:30
unsupported-cc.ll
…
unsupported-image-a16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
unsupported-image-g16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
update-lds-alignment.ll
[AMDGPU] Use performOptimizedStructLayout for LDS sort
2021-06-22 09:58:10 -07:00
update-phi.ll
[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree
2021-01-02 01:01:20 +03:00
urem-seteq-illegal-types.ll
Support {S,U}REMEqFold before legalization
2021-04-01 01:35:41 +03:00
urem.ll
…
urem64.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
use-sgpr-multiple-times.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
usubo.ll
…
usubsat.ll
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
v1i64-kernel-arg.ll
…
v1024.ll
…
v_cndmask.ll
[AMDGPU] Tidy up a FIXME fixed by D34973
2021-02-18 14:28:27 +00:00
v_cvt_pk_u8_f32.ll
…
v_mac.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
v_mac_f16.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
v_madak_f16.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
v_mov_b64_expand_and_shrink.mir
[AMDGPU] Fix immediate sign during V_MOV_B64_PSEUDO expansion
2021-07-01 09:00:29 -07:00
v_mov_b64_expansion.mir
[AMDGPU] Fix immediate sign during V_MOV_B64_PSEUDO expansion
2021-07-01 09:00:29 -07:00
v_pack.ll
[AMDGPU] Improve Codegen for build_vector
2021-05-12 14:17:44 +01:00
v_swap_b32.mir
[AMDGPU] Fix v_swap_b32 formation on physical registers
2021-04-29 20:53:40 +01:00
valu-i1.ll
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
vccz-corrupt-bug-workaround.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
vcmpx-exec-war-hazard.mir
[AMDGPU] Move kill lowering to WQM pass and add live mask tracking
2021-02-11 20:31:29 +09:00
vcmpx-permlane-hazard.mir
[AMDGPU] Move kill lowering to WQM pass and add live mask tracking
2021-02-11 20:31:29 +09:00
vector-alloca-addrspacecast.ll
…
vector-alloca-atomic.ll
…
vector-alloca-bitcast.ll
[InstCombine] use poison as placeholder for undemanded elems
2020-12-28 08:58:15 +09:00
vector-alloca-limits.ll
[AMDGPU] Limit promote alloca to vector with VGPR budget
2020-07-01 15:57:24 -07:00
vector-alloca.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-07 09:48:14 -08:00
vector-extract-insert.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
vector-legalizer-divergence.ll
…
vector_shuffle.packed.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
vectorize-buffer-fat-pointer.ll
…
vectorize-global-local.ll
…
vectorize-loads.ll
[amdgpu] Add the late codegen preparation pass.
2020-10-27 14:07:59 -04:00
verify-constant-bus-violations.mir
[AMDGPU] Consider all SGPR uses as unique in constant bus verify
2020-09-24 10:52:40 +09:00
verify-ds-gws-align.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
verify-duplicate-literal.mir
[AMDGPU] Allow multiple uses of the same literal
2021-04-20 16:44:01 +01:00
verify-gfx90a-aligned-vgprs.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
verify-sop.mir
…
vertex-fetch-encoding.ll
…
vgpr-descriptor-waterfall-loop-idom-update.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
vgpr-liverange-ir.ll
[AMDGPU] Add Optimize VGPR LiveRange Pass.
2021-06-21 15:25:55 +08:00
vgpr-liverange.ll
[AMDGPU] Add Optimize VGPR LiveRange Pass.
2021-06-21 15:25:55 +08:00
vgpr-remat.mir
[AMDGPU] Fix isReallyTriviallyReMaterializable for V_MOV_*
2021-03-10 16:18:12 +00:00
vgpr-spill-dead-frame-in-dbg-value.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vgpr-spill-emergency-stack-slot-compute.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
vgpr-spill-emergency-stack-slot.ll
…
vgpr-spill.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vgpr-tuple-allocation.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
vi-removed-intrinsics.ll
…
virtregrewrite-undef-identity-copy.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
visit-physreg-vgpr-imm-folding-bug.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
vmem-to-salu-hazard.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vmem-vcc-hazard.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
vop-shrink-frame-index.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
vop-shrink-non-ssa.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
vop-shrink.ll
…
vselect.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
vselect64.ll
…
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait.ll
…
waitcnt-agpr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
waitcnt-back-edge-loop.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
waitcnt-debug.mir
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
waitcnt-flat.ll
…
waitcnt-loop-irreducible.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-loop-single-basic-block.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-looptest.ll
[AMDGPU] Optimize waitcnt insertion for flat memory operations
2020-10-20 22:55:12 +00:00
waitcnt-meta-instructions.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-no-redundant.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
waitcnt-overflow.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-permute.mir
…
waitcnt-preexisting-vscnt.mir
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
waitcnt-preexisting.mir
[AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2
2021-05-11 13:17:33 -07:00
waitcnt-skip-meta.mir
[AMDGPU] Skip CFIInstructions in SIInsertWaitcnts
2020-06-17 12:41:03 -04:00
waitcnt-vmem-waw.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
waitcnt-vscnt.ll
[AMDGPU] Optimize waitcnt insertion for flat memory operations
2020-10-20 22:55:12 +00:00
waitcnt-vscnt.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
waitcnt.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wave32.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
wave_dispatch_regs.ll
[AMDGPU] Emit new pal metadata by default
2020-10-26 10:16:17 +01:00
widen-smrd-loads.ll
[DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (REAPPLIED).
2021-01-21 13:01:34 +00:00
widen-vselect-and-mask.ll
…
widen_extending_scalar_loads.ll
…
wqm.ll
[AMDGPU] Fix shortfalls in WQM marking
2021-03-15 21:44:15 +09:00
wqm.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
write-register-vgpr-into-sgpr.ll
…
write_register.ll
…
wrong-transalu-pos-fix.ll
…
wwm-reserved-spill.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
wwm-reserved.ll
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
2021-03-03 09:33:57 +01:00
xfail.r600.bitcast.ll
…
xnack-subtarget-feature-any.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
xnack-subtarget-feature-disabled.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
xnack-subtarget-feature-enabled.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
xnor.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-07 09:48:14 -08:00
xor.ll
…
xor3-i1-const.ll
…
xor3.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
xor_add.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
zero_extend.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-07 09:48:14 -08:00
zext-i64-bit-operand.ll
…
zext-lid.ll
…
