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AsmParser
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RISSCV: clang-format RISC-V AsmParser (NFC)
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2021-05-05 10:16:41 -07:00 |
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Disassembler
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[RISCV] Fix shared libs build
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2021-02-09 06:14:25 -06:00 |
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MCTargetDesc
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[RISCV] Add explanatory comment to RISCVOp::OPERAND_AVL.
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2021-04-28 09:55:36 -07:00 |
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TargetInfo
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llvmbuildectomy - replace llvm-build by plain cmake
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2020-11-13 10:35:24 +01:00 |
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CMakeLists.txt
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[RISCV] Merge Utils library into MCTargetDesc
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2021-01-14 11:47:30 -08:00 |
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RISCV.h
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[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'
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2021-03-16 10:02:35 -07:00 |
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RISCV.td
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[RISCV][NFC] Fix formatting
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2021-04-09 14:41:09 +08:00 |
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RISCVAsmPrinter.cpp
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[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'
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2021-03-16 10:02:35 -07:00 |
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RISCVCallLowering.cpp
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[GlobalISel] Base implementation for sret demotion.
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2021-01-06 10:30:50 +05:30 |
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RISCVCallLowering.h
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[GlobalISel] Base implementation for sret demotion.
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2021-01-06 10:30:50 +05:30 |
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RISCVCallingConv.td
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…
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RISCVCleanupVSETVLI.cpp
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[RISCV] Optimize more redundant VSETVLIs
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2021-04-02 10:04:07 +01:00 |
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RISCVExpandAtomicPseudoInsts.cpp
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…
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RISCVExpandPseudoInsts.cpp
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[RISCV] Spilling for Zvlsseg registers.
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2021-03-19 07:46:16 +08:00 |
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RISCVFrameLowering.cpp
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[RISCV] Fix StackOffset calculation when using sp to access the fixed stack object in the case of rvv vector objects existed
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2021-04-30 11:02:38 +08:00 |
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RISCVFrameLowering.h
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[RISCV] Fix offset computation for RVV
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2021-03-29 17:03:49 +00:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Store SEW in RISCV vector pseudo instructions in log2 form.
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2021-05-02 12:09:20 -07:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Refactor an optimization of addition with immediate
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2021-04-20 18:04:25 +08:00 |
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RISCVISelLowering.cpp
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[RISCV][VP] Lower VP ISD nodes to RVV instructions
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2021-05-05 12:32:24 +01:00 |
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RISCVISelLowering.h
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[RISCV][VP] Lower VP ISD nodes to RVV instructions
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2021-05-05 12:32:24 +01:00 |
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RISCVInstrFormats.td
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[RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension.
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2021-04-15 11:08:28 -07:00 |
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RISCVInstrFormatsC.td
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…
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RISCVInstrFormatsV.td
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[RISCV] Add new vector instructions in v0.10.
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2021-02-03 13:28:58 +08:00 |
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RISCVInstrInfo.cpp
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[RISCV] Fix missing emergency slots for scalable stack offsets
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2021-04-20 09:59:41 +01:00 |
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RISCVInstrInfo.h
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[RISCV] Spilling for Zvlsseg registers.
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2021-03-19 07:46:16 +08:00 |
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RISCVInstrInfo.td
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[RISCV] Optimize addition with immediate
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2021-04-26 13:26:17 +08:00 |
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RISCVInstrInfoA.td
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[RISCV][NFC] Add explicit type i64 to RV64 only patterns.
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2021-04-09 09:37:04 +08:00 |
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RISCVInstrInfoB.td
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[RISCV] [1/2] Add IR intrinsic for Zbe extension
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2021-04-25 19:14:34 -07:00 |
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RISCVInstrInfoC.td
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[RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg.
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2021-03-19 20:39:49 -07:00 |
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RISCVInstrInfoD.td
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[RISCV] Cleanup up the spec version references around fmaxnum/fminnum.
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2021-04-21 14:50:29 -07:00 |
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RISCVInstrInfoF.td
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[RISCV] Cleanup up the spec version references around fmaxnum/fminnum.
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2021-04-21 14:50:29 -07:00 |
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RISCVInstrInfoM.td
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[RISCV] Add custom type legalization to form MULHSU when possible.
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2021-04-01 10:15:55 -07:00 |
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RISCVInstrInfoV.td
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[RISCV] Temporary in vmsge(u).vx pseudo instructions can't be V0.
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2021-04-21 14:50:29 -07:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV] Store SEW in RISCV vector pseudo instructions in log2 form.
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2021-05-02 12:09:20 -07:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV][NFC] Fix up pseudoinstruction name in comment
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2021-05-05 16:40:28 +01:00 |
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RISCVInstrInfoVVLPatterns.td
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[RISCV][NFC] Fix up pseudoinstruction name in comment
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2021-05-05 16:40:28 +01:00 |
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RISCVInstrInfoZfh.td
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[RISCV] Cleanup up the spec version references around fmaxnum/fminnum.
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2021-04-21 14:50:29 -07:00 |
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RISCVInstructionSelector.cpp
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…
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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…
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RISCVMCInstLower.cpp
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[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'
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2021-03-16 10:02:35 -07:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Don't emit save-restore call if function is a interrupt handler
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2021-04-16 12:54:47 +08:00 |
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RISCVMergeBaseOffset.cpp
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[RISCV] Support Zfh half-precision floating-point extension.
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2020-12-03 09:16:33 +08:00 |
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RISCVRegisterBankInfo.cpp
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…
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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[RISCV] Further fixes for RVV stack offset computation
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2021-04-21 10:51:07 +01:00 |
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RISCVRegisterInfo.h
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[RISCV] Improve register allocation around vector masks
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2021-02-20 14:47:51 +00:00 |
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RISCVRegisterInfo.td
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[RISCV] Introduce floating point control and state registers
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2021-04-21 12:55:30 +07:00 |
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RISCVSchedRocket.td
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[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
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2021-03-31 15:06:14 -07:00 |
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RISCVSchedSiFive7.td
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[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
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2021-03-31 15:06:14 -07:00 |
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RISCVSchedule.td
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[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
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2021-03-31 15:06:14 -07:00 |
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RISCVScheduleB.td
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[RISCV] Move scheduling resources for B into a separate file (NFC)
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2021-03-29 20:37:22 -05:00 |
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RISCVSubtarget.cpp
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[RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget.
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2021-04-23 15:06:20 -07:00 |
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RISCVSubtarget.h
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[RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget.
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2021-04-23 15:06:20 -07:00 |
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RISCVSystemOperands.td
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[RISCV] Introduce floating point control and state registers
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2021-04-21 12:55:30 +07:00 |
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RISCVTargetMachine.cpp
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[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.
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2021-03-02 12:55:51 -08:00 |
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RISCVTargetMachine.h
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[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
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2020-12-18 21:50:55 +00:00 |
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RISCVTargetObjectFile.cpp
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ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects
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2021-02-26 16:38:44 -08:00 |
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RISCVTargetObjectFile.h
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…
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RISCVTargetTransformInfo.cpp
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[RISCV] Add support for fmin/fmax vector reductions
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2021-05-03 10:33:51 +01:00 |
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RISCVTargetTransformInfo.h
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[RISCV][VP] Lower VP ISD nodes to RVV instructions
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2021-05-05 12:32:24 +01:00 |
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