llvm-project/llvm/test/CodeGen
Bob Haarman 223303c5a3 Reland r311957 [codeview] support more DW_OPs for more complete debug info
Summary:
Some variables show up in Visual Studio as "optimized out" even in -O0
-Od builds. This change fixes two issues that would cause this to
happen. The first issue is that not all DIExpressions we generate were
recognized by the CodeView writer. This has been addressed by adding
support for DW_OP_constu, DW_OP_minus, and DW_OP_plus. The second
issue is that we had no way to encode DW_OP_deref in CodeView. We get
around that by changinge the type we encode in the debug info to be
a reference to the type in the source code.

This fixes PR34261.

The reland adds two extra checks to the original: It checks if the
DbgVariableLocation is valid before checking any of its fields, and
it only emits ranges with nonzero registers.

Reviewers: aprantl, rnk, zturner

Reviewed By: rnk

Subscribers: mgorny, llvm-commits, aprantl, hiraditya

Differential Revision: https://reviews.llvm.org/D36907

llvm-svn: 312034
2017-08-29 20:59:25 +00:00
..
AArch64 [AArch64][Falkor] Avoid generating STRQro* instructions 2017-08-28 20:48:43 +00:00
AMDGPU [AMDGPU] Fix regression in AMDGPULibCalls allowing native for doubles 2017-08-28 18:00:08 +00:00
ARC [ARC] Add ARC backend. 2017-08-24 15:40:33 +00:00
ARM [ARM] GlobalISel: Select globals in PIC mode 2017-08-29 09:47:55 +00:00
AVR [AVR] Use the correct register classes for 16-bit atomic operations 2017-08-24 00:14:38 +00:00
BPF bpf: add variants of -mcpu=# and support for additional jmp insns 2017-08-23 04:25:57 +00:00
Generic [TargetPassConfig] Feature generic options to setup start/stop-after/before 2017-07-31 18:24:07 +00:00
Hexagon [Hexagon] Check for potential bank conflicts in post-RA scheduling 2017-08-28 18:36:21 +00:00
Inputs
Lanai
MIR Reland r311957 [codeview] support more DW_OPs for more complete debug info 2017-08-29 20:59:25 +00:00
MSP430 [DAG] Improve Aliasing of operations to static alloca 2017-07-18 20:06:24 +00:00
Mips [mips] Generate NMADD and NMSUB instructions when fneg node is present 2017-08-27 21:07:24 +00:00
NVPTX [NVPTX] Add lowering of i128 params. 2017-07-20 21:16:03 +00:00
Nios2
PowerPC [DAG] convert vector select-of-constants to logic/math 2017-08-24 23:24:43 +00:00
SPARC Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" round 2 2017-08-18 01:43:11 +00:00
SystemZ [SystemZ, MachineScheduler] Improve post-RA scheduling. 2017-08-17 08:33:44 +00:00
Thumb [ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting illegal modes 2017-08-24 10:00:25 +00:00
Thumb2 [ARM] Call setBooleanContents(ZeroOrOneBooleanContent) 2017-08-22 11:02:37 +00:00
WebAssembly [WebAssembly] FastISel : Bail to SelectionDAG for constexpr calls 2017-08-24 19:53:44 +00:00
WinEH
X86 [X86] Add a test cases to demonstrate selecting GPR instructions when 2017-08-29 11:58:03 +00:00
XCore Delete Default and JITDefault code models 2017-08-03 02:16:21 +00:00