forked from OSchip/llvm-project
366 lines
13 KiB
TableGen
366 lines
13 KiB
TableGen
//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the Hexagon target.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Hexagon Subtarget features.
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//===----------------------------------------------------------------------===//
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// Hexagon Architectures
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include "HexagonDepArch.td"
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// Hexagon ISA Extensions
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def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
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def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
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[ExtensionHVX]>;
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def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
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[ExtensionHVX,ExtensionHVXV60]>;
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def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
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[ExtensionHVX,ExtensionHVXV60, ExtensionHVXV62]>;
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def ExtensionHVX64B
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: SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true",
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"Hexagon HVX 64B instructions", [ExtensionHVX]>;
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def ExtensionHVX128B
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: SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true",
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"Hexagon HVX 128B instructions", [ExtensionHVX]>;
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// This is an alias to ExtensionHVX128B to accept the hvx-double as
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// an acceptable subtarget feature.
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def ExtensionHVXDbl
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: SubtargetFeature<"hvx-double", "UseHVX128BOps", "true",
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"Hexagon HVX 128B instructions", [ExtensionHVX128B]>;
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def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
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"Use constant-extended calls">;
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def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
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"Supports mem_noshuf feature">;
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def FeatureDuplex : SubtargetFeature<"duplex", "EnableDuplex", "true",
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"Enable generation of duplex instruction">;
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def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
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"true", "Reserve register R19">;
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//===----------------------------------------------------------------------===//
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// Hexagon Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def UseMEMOP : Predicate<"HST->useMemOps()">;
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def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">;
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def UseHVX64B : Predicate<"HST->useHVX64BOps()">,
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AssemblerPredicate<"ExtensionHVX64B">;
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def UseHVX128B : Predicate<"HST->useHVX128BOps()">,
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AssemblerPredicate<"ExtensionHVX128B">;
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def UseHVX : Predicate<"HST->useHVXOps()">,
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AssemblerPredicate<"ExtensionHVXV60">;
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def UseHVXV60 : Predicate<"HST->useHVXOps()">,
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AssemblerPredicate<"ExtensionHVXV60">;
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def UseHVXV62 : Predicate<"HST->useHVXOps()">,
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AssemblerPredicate<"ExtensionHVXV62">;
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def UseHVXV65 : Predicate<"HST->useHVXOps()">,
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AssemblerPredicate<"ExtensionHVXV65">;
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def Hvx64 : HwMode<"+hvx-length64b">;
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def Hvx64old : HwMode<"-hvx-double">;
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def Hvx128 : HwMode<"+hvx-length128b">;
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def Hvx128old : HwMode<"+hvx-double">;
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//===----------------------------------------------------------------------===//
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// Classes used for relation maps.
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//===----------------------------------------------------------------------===//
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class ImmRegShl;
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// ImmRegRel - Filter class used to relate instructions having reg-reg form
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// with their reg-imm counterparts.
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class ImmRegRel;
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// PredRel - Filter class used to relate non-predicated instructions with their
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// predicated forms.
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class PredRel;
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// PredNewRel - Filter class used to relate predicated instructions with their
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// predicate-new forms.
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class PredNewRel: PredRel;
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// NewValueRel - Filter class used to relate regular store instructions with
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// their new-value store form.
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class NewValueRel: PredNewRel;
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// NewValueRel - Filter class used to relate load/store instructions having
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// different addressing modes with each other.
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class AddrModeRel: NewValueRel;
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class PostInc_BaseImm;
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class IntrinsicsRel;
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate non-predicate instructions with their
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// predicated formats - true and false.
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//
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def getPredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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// Instructions with the same BaseOpcode and isNVStore values form a row.
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let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
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// Instructions with the same predicate sense form a column.
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let ColFields = ["PredSense"];
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// The key column is the unpredicated instructions.
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let KeyCol = [""];
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// Value columns are PredSense=true and PredSense=false
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let ValueCols = [["true"], ["false"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicate-true instructions with their
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// predicate-false forms
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//
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def getFalsePredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
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let ColFields = ["PredSense"];
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let KeyCol = ["true"];
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let ValueCols = [["false"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicate-false instructions with their
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// predicate-true forms
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//
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def getTruePredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
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let ColFields = ["PredSense"];
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let KeyCol = ["false"];
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let ValueCols = [["true"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicated instructions with their .new
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// format.
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//
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def getPredNewOpcode : InstrMapping {
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let FilterClass = "PredNewRel";
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let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
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let ColFields = ["PNewValue"];
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let KeyCol = [""];
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let ValueCols = [["new"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate .new predicated instructions with their old
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// format.
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//
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def getPredOldOpcode : InstrMapping {
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let FilterClass = "PredNewRel";
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let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
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let ColFields = ["PNewValue"];
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let KeyCol = ["new"];
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let ValueCols = [[""]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate store instructions with their new-value
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// format.
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//
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def getNewValueOpcode : InstrMapping {
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let FilterClass = "NewValueRel";
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let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
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let ColFields = ["NValueST"];
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let KeyCol = ["false"];
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let ValueCols = [["true"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate new-value store instructions with their old
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// format.
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//
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def getNonNVStore : InstrMapping {
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let FilterClass = "NewValueRel";
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let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
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let ColFields = ["NValueST"];
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let KeyCol = ["true"];
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let ValueCols = [["false"]];
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}
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def changeAddrMode_abs_io: InstrMapping {
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let FilterClass = "AddrModeRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
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"isFloat"];
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let ColFields = ["addrMode"];
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let KeyCol = ["Absolute"];
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let ValueCols = [["BaseImmOffset"]];
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}
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def changeAddrMode_io_abs: InstrMapping {
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let FilterClass = "AddrModeRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
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"isFloat"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseImmOffset"];
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let ValueCols = [["Absolute"]];
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}
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def changeAddrMode_io_rr: InstrMapping {
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let FilterClass = "AddrModeRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseImmOffset"];
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let ValueCols = [["BaseRegOffset"]];
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}
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def changeAddrMode_rr_io: InstrMapping {
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let FilterClass = "AddrModeRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseRegOffset"];
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let ValueCols = [["BaseImmOffset"]];
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}
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def changeAddrMode_pi_io: InstrMapping {
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let FilterClass = "PostInc_BaseImm";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["PostInc"];
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let ValueCols = [["BaseImmOffset"]];
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}
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def changeAddrMode_io_pi: InstrMapping {
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let FilterClass = "PostInc_BaseImm";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseImmOffset"];
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let ValueCols = [["PostInc"]];
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}
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def changeAddrMode_rr_ur: InstrMapping {
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let FilterClass = "ImmRegShl";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseRegOffset"];
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let ValueCols = [["BaseLongOffset"]];
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}
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def changeAddrMode_ur_rr : InstrMapping {
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let FilterClass = "ImmRegShl";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseLongOffset"];
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let ValueCols = [["BaseRegOffset"]];
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}
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def getRegForm : InstrMapping {
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let FilterClass = "ImmRegRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
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let ColFields = ["InputType"];
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let KeyCol = ["imm"];
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let ValueCols = [["reg"]];
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}
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def notTakenBranchPrediction : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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let ColFields = ["isBrTaken"];
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let KeyCol = ["true"];
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let ValueCols = [["false"]];
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}
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def takenBranchPrediction : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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let ColFields = ["isBrTaken"];
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let KeyCol = ["false"];
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let ValueCols = [["true"]];
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}
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def getRealHWInstr : InstrMapping {
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let FilterClass = "IntrinsicsRel";
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let RowFields = ["BaseOpcode"];
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let ColFields = ["InstrType"];
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let KeyCol = ["Pseudo"];
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let ValueCols = [["Pseudo"], ["Real"]];
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}
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//===----------------------------------------------------------------------===//
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// Register File, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "HexagonSchedule.td"
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include "HexagonRegisterInfo.td"
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include "HexagonOperands.td"
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include "HexagonDepOperands.td"
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include "HexagonDepITypes.td"
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include "HexagonInstrFormats.td"
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include "HexagonDepInstrFormats.td"
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include "HexagonDepInstrInfo.td"
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include "HexagonCallingConv.td"
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include "HexagonPseudo.td"
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include "HexagonPatterns.td"
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include "HexagonPatternsHVX.td"
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include "HexagonPatternsV65.td"
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include "HexagonDepMappings.td"
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include "HexagonIntrinsics.td"
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include "HexagonMapAsm2IntrinV62.gen.td"
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include "HexagonMapAsm2IntrinV65.gen.td"
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def HexagonInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Hexagon processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, SchedMachineModel Model,
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list<SubtargetFeature> Features>
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: ProcessorModel<Name, Model, Features>;
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def : Proc<"hexagonv4", HexagonModelV4,
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[ArchV4, FeatureDuplex]>;
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def : Proc<"hexagonv5", HexagonModelV4,
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[ArchV4, ArchV5, FeatureDuplex]>;
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def : Proc<"hexagonv55", HexagonModelV55,
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[ArchV4, ArchV5, ArchV55, FeatureDuplex]>;
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def : Proc<"hexagonv60", HexagonModelV60,
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[ArchV4, ArchV5, ArchV55, ArchV60, FeatureDuplex]>;
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def : Proc<"hexagonv62", HexagonModelV62,
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[ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, FeatureDuplex]>;
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def : Proc<"hexagonv65", HexagonModelV65,
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[ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
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FeatureMemNoShuf, FeatureDuplex]>;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def HexagonAsmParser : AsmParser {
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let ShouldEmitMatchRegisterAltName = 1;
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bit HasMnemonicFirst = 0;
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}
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def HexagonAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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string TokenizingCharacters = "#()=:.<>!+*-|^&";
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string BreakCharacters = "";
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}
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def HexagonAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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bit isMCAsmWriter = 1;
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}
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def Hexagon : Target {
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let InstructionSet = HexagonInstrInfo;
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let AssemblyParsers = [HexagonAsmParser];
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let AssemblyParserVariants = [HexagonAsmParserVariant];
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let AssemblyWriters = [HexagonAsmWriter];
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let AllowRegisterRenaming = 1;
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}
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