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Simon Dardis d32a2d30cb [inlineasm] Propagate operand constraints to the backend 
When SelectionDAGISel transforms a node representing an inline asm
block, memory constraint information is not preserved. This can cause
constraints to be broken when a memory offset is of the form:

offset + frame index

when the frame is resolved.

By propagating the constraints all the way to the backend, targets can
enforce memory operands of inline assembly to conform to their constraints.

For MIPSR6, some instructions had their offsets reduced to 9 bits from
16 bits such as ll/sc. This becomes problematic when using inline assembly
to perform atomic operations, as an offset can generated that is too big to
encode in the instruction.

Reviewers: dsanders, vkalintris

Differential Review: https://reviews.llvm.org/D21615

llvm-svn: 275786
 		2016-07-18 13:17:31 +00:00
..
Fast-ISel [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
cconv [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 2016-07-11 07:41:56 +00:00
compactbranches [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
cstmaterialization [mips] Missing test case 2016-06-15 13:49:58 +00:00
llvm-ir [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
mips32r6
…
mips64r6 [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
msa [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
2008-06-05-Carry.ll
…
2008-07-03-SRet.ll [opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction 2015-02-27 19:29:02 +00:00
2008-07-06-fadd64.ll
…
2008-07-07-FPExtend.ll
…
2008-07-07-Float2Int.ll
…
2008-07-07-IntDoubleConvertions.ll
…
2008-07-15-InternalConstant.ll [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
2008-07-15-SmallSection.ll [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
2008-07-16-SignExtInReg.ll
…
2008-07-22-Cstpool.ll
…
2008-07-23-fpcmp.ll
…
2008-07-29-icmp.ll
…
2008-07-31-fcopysign.ll
…
2008-08-01-AsmInline.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
2008-08-03-ReturnDouble.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
2008-08-03-fabs64.ll
…
2008-08-04-Bitconvert.ll
…
2008-08-06-Alloca.ll
…
2008-08-07-CC.ll
…
2008-08-07-FPRound.ll
…
2008-08-08-bswap.ll
…
2008-08-08-ctlz.ll
…
2008-10-13-LegalizerBug.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
2008-11-10-xint_to_fp.ll Now that we have a soft-float attribute, use it instead of the 2015-05-08 00:57:22 +00:00
2009-11-16-CstPoolLoad.ll Move the Mips target to storing the ABI in the TargetMachine rather 2015-01-26 17:33:46 +00:00
2010-07-20-Switch.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
2010-11-09-CountLeading.ll
…
2010-11-09-Mul.ll
…
2011-05-26-BranchKillsVreg.ll
…
2012-12-12-ExpandMemcpy.ll Revert "Change memcpy/memset/memmove to have dest and source alignments." 2015-11-19 05:56:52 +00:00
2013-11-18-fp64-const0.ll
…
DbgValueOtherTargets.test
…
abicalls.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
abiflags-xx.ll
…
abiflags32.ll Move the Mips target to storing the ABI in the TargetMachine rather 2015-01-26 17:33:46 +00:00
addc.ll
…
addi.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
addressing-mode.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
adjust-callstack-sp.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
align16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
alloca.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
alloca16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
analyzebranch.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
and1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
asm-large-immediate.ll [mips][ias] Explicitly disable IAS on asm-large-immediate.ll. 2015-11-13 13:02:31 +00:00
assertzext-trunc.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
atomic.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
atomicCmpSwapPW.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
atomicops.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
beqzc.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
beqzc1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
biggot.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
blez_bgez.ll Revert "[mips] Promote the result of SETCC nodes to GPR width." 2016-03-01 20:25:43 +00:00
blockaddr.ll Revert r237789 - [mips] The naming convention for private labels is ABI dependant. 2015-05-20 14:18:59 +00:00
br-jmp.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconeq.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconeqk.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconeqz.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconge.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brcongt.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconle.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconlt.ll [mips][microMIPS] Revert commit r267137 2016-04-25 15:40:08 +00:00
brconne.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconnek.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brconnez.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brdelayslot.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
brind.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
brsize3.ll [mips][mips16] Use isUnconditionalBranch() in AnalyzeBranch() and constant island pass. 2016-05-06 13:23:51 +00:00
brsize3a.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
bswap.ll [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... 2014-11-07 16:54:21 +00:00
buildpairextractelementf64.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
cache-intrinsic.ll [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
call-optimization.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
cannot-copy-registers.ll [mips][microMIPS] Fix for "Cannot copy registers" assertion 2016-04-13 06:17:21 +00:00
cfi_offset.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
check-adde-redundant-moves.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
check-noat.ll
…
ci2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
cmov.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
cmplarge.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
const-mult.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
const1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
const4a.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
const6.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
const6a.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
constantfp0.ll
…
countleading.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
cprestore.ll
…
ctlz-v.ll [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... 2014-11-07 16:54:21 +00:00
ctlz.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
cttz-v.ll [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... 2014-11-07 16:54:21 +00:00
dagcombine_crash.ll Use FileCheck for test 2015-04-13 18:47:19 +00:00
delay-slot-fill-forward.ll [mips] Do not place users of $ra in the delay slot of call instructions. 2015-05-14 13:17:56 +00:00
delay-slot-kill.ll Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions. 2015-08-04 14:26:35 +00:00
disable-tail-merge.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
div.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
div_rem.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
divrem.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
divu.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
divu_remu.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
double2int.ll
…
dsp-patterns-cmp-vselect.ll
…
dsp-patterns.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
dsp-r1.ll [mips][dsp] Fix use without def on DSPCtrl registers read by rddsp intrinsic. 2016-06-14 09:29:46 +00:00
dsp-r2.ll
…
dsp-vec-load-store.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
dynamic-stack-realignment.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
eh-dwarf-cfa.ll [mips] Optimize stack pointer adjustments. 2016-06-14 13:39:43 +00:00
eh-return32.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
eh-return64.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
eh.ll Codegen: Fix broken assumption in Tail Merge. 2016-06-24 18:16:36 +00:00
ehframe-indirect.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
elf_eflags.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
emergency-spill-slot-near-fp.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
emit-big-cst.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
emutls_generic.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
ex2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
extins.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
f16abs.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
fabs.ll
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fastcc.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
fcmp.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
fcopysign-f32-f64.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
fcopysign.ll [mips] Make isel select the correct DEXT variant up front. 2016-02-29 15:26:54 +00:00
fixdfsf.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
fmadd1.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
fneg.ll
…
fp-indexed-ls.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
fp-spill-reload.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
fp16-promote.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
fp16instrinsmc.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
fp16mix.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
fp16static.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
fp64a.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
fpbr.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
fpneeded.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
fpnotneeded.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
fpxx.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
frame-address.ll
…
frem.ll
…
global-address.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
global-pointer-reg.ll
…
gpreg-lazy-binding.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
gprestore.ll [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
helloworld.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
hf1_body.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
hf16_1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
hf16call32.ll [mips] Enable IAS by default for 32-bit MIPS targets (O32). 2016-05-14 12:43:08 +00:00
hf16call32_body.ll [mips] Enable IAS by default for 32-bit MIPS targets (O32). 2016-05-14 12:43:08 +00:00
hfptrcall.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
i32k.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
i64arg.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
imm.ll
…
indirectcall.ll
…
init-array.ll
…
inlineasm-assembler-directives.ll [mips][ias] Replace invalid assembly insn in test since IAS parses inline assembly. 2015-11-13 11:44:00 +00:00
inlineasm-cnstrnt-bad-I-1.ll
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inlineasm-cnstrnt-bad-J.ll
…
inlineasm-cnstrnt-bad-K.ll
…
inlineasm-cnstrnt-bad-L.ll
…
inlineasm-cnstrnt-bad-N.ll
…
inlineasm-cnstrnt-bad-O.ll
…
inlineasm-cnstrnt-bad-P.ll
…
inlineasm-cnstrnt-reg.ll [mips][ias] Allow whitespace after commas in inlineasm*.ll tests. 2015-11-16 14:14:59 +00:00
inlineasm-cnstrnt-reg64.ll [mips][ias] Allow whitespace after commas in inlineasm*.ll tests. 2015-11-16 14:14:59 +00:00
inlineasm-constraint_ZC_2.ll [inlineasm] Propagate operand constraints to the backend 2016-07-18 13:17:31 +00:00
inlineasm-operand-code.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
inlineasm64.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
inlineasm_constraint.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
inlineasm_constraint_R.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
inlineasm_constraint_ZC.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
inlineasm_constraint_m.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
inlineasmmemop.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
insn-zero-size-bb.ll Enhance BranchProbabilityInfo::calcUnreachableHeuristics for InvokeInst 2015-12-21 22:00:51 +00:00
int-to-float-conversion.ll
…
internalfunc.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
interrupt-attr-64-error.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
interrupt-attr-args-error.ll [mips] Check for the correct error message in tests for interrupt attributes. 2015-10-26 14:24:30 +00:00
interrupt-attr-error.ll [mips] Check for the correct error message in tests for interrupt attributes. 2015-10-26 14:24:30 +00:00
interrupt-attr.ll [mips] Interrupt attribute support for mips32r2+. 2015-10-26 12:38:43 +00:00
jtstat.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
l3mc.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
largeimm1.ll [mips] Optimize stack pointer adjustments. 2016-06-14 13:39:43 +00:00
largeimmprinting.ll [mips] Optimize stack pointer adjustments. 2016-06-14 13:39:43 +00:00
lazy-binding.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
lb1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lbu1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lcb2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lcb3c.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lcb4a.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lcb5.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
lh1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lhu1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
lit.local.cfg
…
llcarry.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
load-store-left-right.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
longbranch.ll [mips] Emit a JALR with $rd equal to $zero, instead of a JR in MIPS32R6. 2016-06-18 15:39:43 +00:00
lw16-base-reg.ll [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions 2016-06-27 08:23:28 +00:00
machineverifier.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
madd-msub.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
mature-mc-support.ll
…
mbrsize4a.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
memcpy.ll Revert "Change memcpy/memset/memmove to have dest and source alignments." 2015-11-19 05:56:52 +00:00
micromips-addiu.ll [mips][micromips] Make getPointerRegClass() result depend on the instruction. 2016-05-09 13:38:25 +00:00
micromips-addu16.ll [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator 2015-03-04 15:47:42 +00:00
micromips-and16.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-andi.ll [mips][microMIPS] Revert commits r264245 and r264248. 2016-04-02 23:06:13 +00:00
micromips-atomic.ll [mips][microMIPS] This patch implements functionality in MIPS delay slot 2014-11-21 22:04:35 +00:00
micromips-atomic1.ll [llvm-objdump] Support detection of feature bits from the object and implement this for Mips. 2016-06-16 09:17:03 +00:00
micromips-compact-branches.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-compact-jump.ll [mips][microMIPS] Delay slot filler: Replace the microMIPS JR with the JRC 2015-02-13 17:51:27 +00:00
micromips-delay-slot-jr.ll [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
micromips-delay-slot.ll [mips][microMIPS] Delay slot filler modifications 2016-03-23 10:29:38 +00:00
micromips-directives.ll
…
micromips-gp-rc.ll [mips][microMIPS] Revert commits r264245 and r264248. 2016-04-02 23:06:13 +00:00
micromips-jal.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-li.ll [mips][microMIPS] Implement CodeGen support for LI16 instruction. 2014-12-11 13:56:23 +00:00
micromips-load-effective-address.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-lwc1-swc1.ll [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 2016-07-11 07:41:56 +00:00
micromips-not16.ll [mips][microMIPS] Make usage of NOT16 by code generator 2015-03-11 20:28:31 +00:00
micromips-or16.ll [mips][microMIPS] Prevent usage of OR16_MMR6 instruction when code for microMIPS is generated. 2016-03-04 17:34:31 +00:00
micromips-rdhwr-directives.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-shift.ll [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions 2016-04-27 11:02:23 +00:00
micromips-subu16.ll [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator 2015-03-04 15:47:42 +00:00
micromips-sw-lw-16.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
micromips-xor16.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
mips-shf-gprel.s [MC][ELF] Handle MIPS specific .sdata and .sbss directives 2016-02-11 06:45:54 +00:00
mips16-hf-attr-2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16-hf-attr.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_3.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_4.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_5.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_6.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_7.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_32_8.ll [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
mips16_32_9.ll
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mips16_32_10.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16_fpret.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16ex.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mips16fpe.ll [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier. 2016-05-19 10:42:14 +00:00
mips64-f128-call.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
mips64-f128.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
mips64-libcall.ll Now that we have a soft-float attribute, use it instead of the 2015-05-08 00:57:22 +00:00
mips64-sret.ll Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. 2015-02-26 12:29:48 +00:00
mips64directive.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
mips64ext.ll Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. 2015-02-26 12:29:48 +00:00
mips64extins.ll [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
mips64fpimm0.ll Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. 2015-02-26 12:29:48 +00:00
mips64fpldst.ll [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 2016-07-11 07:41:56 +00:00
mips64imm.ll
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mips64instrs.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
mips64intldst.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
mips64lea.ll
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mips64muldiv.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
mips64shift.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
mips64signextendsesf.ll Now that we have a soft-float attribute, use it instead of the 2015-05-08 00:57:22 +00:00
mips64sinttofpsf.ll Now that we have a soft-float attribute, use it instead of the 2015-05-08 00:57:22 +00:00
mipslopat.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
misha.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mno-ldc1-sdc1.ll [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 2016-07-11 07:41:56 +00:00
mul.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mulll.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
mulull.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
nacl-align.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
nacl-branch-delay.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
nacl-reserved-regs.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
named-register-n32.ll Move the Mips target to storing the ABI in the TargetMachine rather 2015-01-26 17:33:46 +00:00
named-register-n64.ll [mips] Add support for accessing $gp as a named register. 2015-01-09 17:21:30 +00:00
named-register-o32.ll [mips] Add support for accessing $gp as a named register. 2015-01-09 17:21:30 +00:00
neg1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
no-odd-spreg-msa.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
no-odd-spreg.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
nomips16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
not1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
null-streamer.ll
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null.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
o32_cc.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
o32_cc_byval.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
o32_cc_vararg.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
octeon.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
octeon_popcnt.ll [mips] Sign-extend i32 values truncated from previously zero-extended i32 values. 2016-04-13 15:07:45 +00:00
optimize-fp-math.ll
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optimize-pic-o0.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
or1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
powif64_16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
prevent-hoisting.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
private-addr.ll Mips: Fix access to private functions. 2016-06-27 03:19:40 +00:00
private.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
ra-allocatable.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
rdhwr-directives.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
rem.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
remat-immed-load.ll Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. 2015-02-26 12:29:48 +00:00
remu.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
return-vector.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
return_address.ll
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rotate.ll [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions 2016-05-04 12:02:12 +00:00
s2rem.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sb1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sel1c.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sel2c.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selTBteqzCmpi.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selTBtnezCmpi.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selTBtnezSlti.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
select.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
selectcc.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
selectiondag-optlevel.ll [mips] SelectionDAGISel subclasses now follow the optimization level. 2016-07-14 13:25:22 +00:00
seleq.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
seleqk.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selgek.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selgt.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selle.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selltk.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selne.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selnek.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
selpat.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setcc-se.ll
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seteq.ll [mips][microMIPS] Revert commit r267137 2016-04-25 15:40:08 +00:00
seteqz.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setge.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setgek.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setle.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setlt.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setltk.ll [mips][microMIPS] Revert commit r267137 2016-04-25 15:40:08 +00:00
setne.ll [mips][microMIPS] Revert commit r267137 2016-04-25 15:40:08 +00:00
setuge.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setugt.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setule.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setult.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
setultk.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sh1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
shift-parts.ll
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simplebr.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sint-fp-store_pattern.ll
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sitofp-selectcc-opt.ll AsmPrinter: Use emitGlobalConstantFP to emit elements of constant data 2015-12-08 02:37:48 +00:00
sll1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sll2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
small-section-reserve-gp.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
spill-copy-acreg.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
sr1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sra1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sra2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
srl1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
srl2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
stack-alignment.ll
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stackcoloring.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
stacksize.ll
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start-asm-file.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
stchar.ll [mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores. 2016-06-16 10:20:59 +00:00
stldst.ll [mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores. 2016-06-16 10:20:59 +00:00
sub1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
sub2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
swzero.ll [opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction 2015-02-27 19:29:02 +00:00
tail16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
tailcall.ll [mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores. 2016-06-16 10:20:59 +00:00
thread-pointer.ll [Mips] Add support for llvm.thread.pointer intrinsic. 2016-04-27 17:21:49 +00:00
tls-alias.ll [opaque pointer type] Add textual IR support for explicit type parameter for global aliases 2015-09-11 03:22:04 +00:00
tls-models.ll [mips] Make Static a default relocation model for MIPS codegen 2016-04-11 15:24:23 +00:00
tls.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
tls16.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
tls16_2.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
tnaked.ll
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trap.ll
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trap1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
uitofp.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
ul1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
unalignedload.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00
vector-load-store.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
vector-setcc.ll [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 2015-02-27 21:17:42 +00:00
weak.ll
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xor1.ll [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
zeroreg.ll [mips] Use --check-prefixes where appropriate. NFC. 2016-06-24 12:23:17 +00:00