llvm-project/llvm/lib/CodeGen
Duncan P. N. Exon Smith ebcce78f65 CodeGen: Remove an iterator => pointer conversion, NFC
Part of PR26753.

llvm-svn: 262154
2016-02-27 20:27:44 +00:00
..
AsmPrinter CodeGen: Change MachineInstr to use MachineInstr&, NFC 2016-02-27 20:01:33 +00:00
GlobalISel [GlobalISel] Fix a ranlib warning about empty TOC. 2016-02-26 20:05:02 +00:00
MIRParser Remove autoconf support 2016-01-26 21:29:08 +00:00
SelectionDAG DAGCombiner: Don't unnecessarily swap operands in ReassociateOps 2016-02-27 19:57:45 +00:00
AggressiveAntiDepBreaker.cpp CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC 2016-02-27 19:33:37 +00:00
AggressiveAntiDepBreaker.h CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC 2016-02-27 19:33:37 +00:00
AllocationOrder.cpp TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints() 2015-07-15 22:16:00 +00:00
AllocationOrder.h TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints() 2015-07-15 22:16:00 +00:00
Analysis.cpp One more batch of self-containing headers. 2016-01-27 19:29:56 +00:00
AntiDepBreaker.h CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC 2016-02-27 19:33:37 +00:00
AtomicExpandPass.cpp ARM: sink atomic release barrier as far as possible into cmpxchg. 2016-02-22 20:55:50 +00:00
BasicTargetTransformInfo.cpp constify the Function parameter to the TTI creation callback and 2015-09-16 23:38:13 +00:00
BranchFolding.cpp CodeGen: Remove an iterator => pointer conversion, NFC 2016-02-27 20:27:44 +00:00
BranchFolding.h [WinEH] Permit branch folding in the face of funclets 2015-10-04 02:22:52 +00:00
BuiltinGCs.cpp [GC] Consolidate all built in GCs into a single file [NFC] 2016-01-19 03:57:18 +00:00
CMakeLists.txt [CMake] Produce an empty library for GlobalISel when not building it. 2016-02-11 19:18:27 +00:00
CalcSpillWeights.cpp CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFC 2016-02-27 20:14:29 +00:00
CallingConvLower.cpp Avoid unnecessary stack realignment in musttail thunks with SSE2 enabled 2016-01-21 22:23:22 +00:00
CodeGen.cpp Move SafeStack to CodeGen. 2016-01-27 16:53:42 +00:00
CodeGenPrepare.cpp [CodeGenPrepare] Remove load-based heuristic 2016-02-25 00:23:27 +00:00
CriticalAntiDepBreaker.cpp CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC 2016-02-27 19:33:37 +00:00
CriticalAntiDepBreaker.h CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC 2016-02-27 19:33:37 +00:00
DFAPacketizer.cpp CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC 2016-02-27 19:09:00 +00:00
DeadMachineInstructionElim.cpp Save LaneMask with livein registers 2015-09-09 18:08:03 +00:00
DwarfEHPrepare.cpp Move EH-specific helper functions to a more appropriate place 2015-12-02 23:06:39 +00:00
EarlyIfConversion.cpp Reapply "CodeGen: Use references in MachineTraceMetrics::Trace, NFC" 2016-02-22 03:33:28 +00:00
EdgeBundles.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
ExecutionDepsFix.cpp use range-based for-loops; NFCI 2015-12-29 17:15:22 +00:00
ExpandISelPseudos.cpp CodeGen: Remove a few more ilist iterator implicit conversions, NFC 2015-10-09 18:44:40 +00:00
ExpandPostRAPseudos.cpp
FaultMaps.cpp Revert "[FaultMaps] Move FaultMapParser to Object/" 2015-06-23 20:09:03 +00:00
FuncletLayout.cpp [WinEH] Update CATCHRET's operand to match its successor 2015-10-05 20:09:16 +00:00
GCMetadata.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
GCMetadataPrinter.cpp Revert 258157 2016-01-19 18:41:10 +00:00
GCRootLowering.cpp [opaque pointer types] Alloca: use getAllocatedType() instead of getType()->getPointerElementType(). 2016-01-18 00:10:01 +00:00
GCStrategy.cpp Revert 258157 2016-01-19 18:41:10 +00:00
GlobalMerge.cpp Make some headers self-contained, remove unused includes that violate layering. 2016-01-27 16:05:37 +00:00
IfConversion.cpp CodeGen: Change MachineInstr to use MachineInstr&, NFC 2016-02-27 20:01:33 +00:00
ImplicitNullChecks.cpp [ImplicitNulls] Add some clarifying comments; NFC 2015-11-13 08:14:00 +00:00
InlineSpiller.cpp CodeGen: Use MachineInstr& in InlineSpiller::rematerializeFor() 2016-02-27 20:23:14 +00:00
InterferenceCache.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
InterferenceCache.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
InterleavedAccessPass.cpp [ARM][AArch64] Turn on by default interleaved access lowering 2015-09-01 11:12:35 +00:00
IntrinsicLowering.cpp getParent() ^ 3 == getModule() ; NFCI 2015-12-14 17:24:23 +00:00
LLVMBuild.txt Include ProfileData as CodeGen's required library. 2016-02-22 22:54:14 +00:00
LLVMTargetMachine.cpp When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
LatencyPriorityQueue.cpp
LexicalScopes.cpp IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
LiveDebugValues.cpp Speed up LiveDebugValues 2016-01-10 18:08:32 +00:00
LiveDebugVariables.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
LiveDebugVariables.h Erase unused FunctionDIs variables after r252219. 2015-11-07 10:21:25 +00:00
LiveInterval.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
LiveIntervalAnalysis.cpp CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFC 2016-02-27 20:14:29 +00:00
LiveIntervalUnion.cpp
LivePhysRegs.cpp WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC 2016-02-27 17:05:33 +00:00
LiveRangeCalc.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
LiveRangeCalc.h TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC 2015-09-25 21:51:14 +00:00
LiveRangeEdit.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
LiveRegMatrix.cpp TargetRegisterInfo: Introduce PrintLaneMask. 2015-09-25 21:51:24 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Annotate dump() methods with LLVM_DUMP_METHOD, addressing Richard Smith r259192 post commit comment. 2016-01-29 20:50:44 +00:00
LocalStackSlotAllocation.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
LowerEmuTLS.cpp Move passes that live in lib/CodeGen out of Scalar.h 2016-01-27 16:05:42 +00:00
MIRPrinter.cpp Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces. 2015-12-01 05:29:22 +00:00
MIRPrinter.h MIR Serialization: move the MIR printer out of the MIR printing pass. 2015-06-15 23:52:35 +00:00
MIRPrintingPass.cpp Re-commit r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes" 2015-09-10 16:49:58 +00:00
MachineBasicBlock.cpp WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC 2016-02-27 17:05:33 +00:00
MachineBlockFrequencyInfo.cpp CodeGen: Avoid ilist iterator implicit conversions in a few more places, NFC 2015-10-09 19:23:20 +00:00
MachineBlockPlacement.cpp Partially revert "Add command line options to force function/loop alignments." 2016-01-21 18:49:15 +00:00
MachineBranchProbabilityInfo.cpp Use getEdgeProbability() instead of getEdgeWeight() in BFI and remove getEdgeWeight() interfaces from MBPI. 2015-12-18 21:53:24 +00:00
MachineCSE.cpp rangify; NFCI 2016-01-06 00:45:42 +00:00
MachineCombiner.cpp Minor code cleanup. NFC. 2016-02-27 01:10:43 +00:00
MachineCopyPropagation.cpp MachineCopyPropagation: Catch copies of the form A<-B;A<-B 2016-02-26 03:18:55 +00:00
MachineDominanceFrontier.cpp
MachineDominators.cpp Remove macro guards for extern template instantiations. 2015-07-13 17:21:31 +00:00
MachineFunction.cpp [X86] Create mergeable constant pool entries for AVX 2016-02-22 22:23:11 +00:00
MachineFunctionAnalysis.cpp MIR Serialization: Connect the machine function analysis pass to the MIR parser. 2015-06-15 20:30:22 +00:00
MachineFunctionPass.cpp Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC 2016-02-25 17:54:15 +00:00
MachineFunctionPrinterPass.cpp Recommit r256952 "Filtering IR printing for print-after-all/print-before-all" 2016-01-06 22:55:03 +00:00
MachineInstr.cpp CodeGen: Change MachineInstr to use MachineInstr&, NFC 2016-02-27 20:01:33 +00:00
MachineInstrBundle.cpp MachineInstrBundle: Fix reversed isSuperRegisterEq() call 2016-01-05 00:45:35 +00:00
MachineLICM.cpp rangify; NFCI 2016-01-06 23:45:05 +00:00
MachineLoopInfo.cpp ADT: Remove == and != comparisons between ilist iterators and pointers 2016-02-21 20:39:50 +00:00
MachineModuleInfo.cpp Remove uses of builtin comma operator. 2016-02-18 22:09:30 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC 2016-02-25 17:54:15 +00:00
MachineRegisterInfo.cpp [GlobalISel][MachineRegisterInfo] Add a method to create generic vregs. 2016-02-11 00:19:17 +00:00
MachineSSAUpdater.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
MachineScheduler.cpp CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFC 2016-02-27 20:14:29 +00:00
MachineSink.cpp Remove uses of builtin comma operator. 2016-02-18 22:09:30 +00:00
MachineTraceMetrics.cpp Reapply "CodeGen: Use references in MachineTraceMetrics::Trace, NFC" 2016-02-22 03:33:28 +00:00
MachineVerifier.cpp WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC 2016-02-27 17:05:33 +00:00
OptimizePHIs.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
PHIElimination.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
PHIEliminationUtils.cpp [WinEH] Add some support for code generating catchpad 2015-08-27 23:27:47 +00:00
PHIEliminationUtils.h
ParallelCG.cpp Add to the split module utility an SCC based method which allows not to globalize any local variables. 2016-01-18 21:07:13 +00:00
Passes.cpp Remove extra whitespace. NFC. 2016-01-18 06:42:51 +00:00
PeepholeOptimizer.cpp fix formatting; NFC 2015-12-29 19:34:53 +00:00
PostRASchedulerList.cpp CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC 2016-02-27 19:33:37 +00:00
ProcessImplicitDefs.cpp Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC" 2016-02-22 20:49:58 +00:00
PrologEpilogInserter.cpp Implemented stack symbol table ordering/packing optimization to improve data locality and code size from SP/FP offset encoding. 2016-02-15 23:44:13 +00:00
PseudoSourceValue.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
README.txt
RegAllocBase.cpp
RegAllocBase.h
RegAllocBasic.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
RegAllocFast.cpp [RegAllocFast] Properly track the physical register definitions on calls. 2016-02-20 00:32:29 +00:00
RegAllocGreedy.cpp Remove uses of builtin comma operator. 2016-02-18 22:09:30 +00:00
RegAllocPBQP.cpp Annotate dump() methods with LLVM_DUMP_METHOD, addressing Richard Smith r259192 post commit comment. 2016-01-29 20:50:44 +00:00
RegisterClassInfo.cpp
RegisterCoalescer.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
RegisterCoalescer.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
RegisterPressure.cpp WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC 2016-02-27 17:05:33 +00:00
RegisterScavenging.cpp TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC 2015-09-25 21:51:14 +00:00
SafeStack.cpp [safestack] Make sure the unsafe stack pointer is popped in all cases 2016-02-02 01:03:11 +00:00
ScheduleDAG.cpp MachineScheduler: Add regpressure information to debug dump 2015-11-06 20:59:02 +00:00
ScheduleDAGInstrs.cpp WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC 2016-02-27 17:05:33 +00:00
ScheduleDAGPrinter.cpp Make the SelectionDAG graph printer use SDNode::PersistentId labels. 2015-10-27 23:09:03 +00:00
ScoreboardHazardRecognizer.cpp Annotate dump() methods with LLVM_DUMP_METHOD, addressing Richard Smith r259192 post commit comment. 2016-01-29 20:50:44 +00:00
ShadowStackGCLowering.cpp [GC] Consolidate all built in GCs into a single file [NFC] 2016-01-19 03:57:18 +00:00
ShrinkWrap.cpp [ShrinkWrapping] Give up on irreducible CFGs. 2016-01-07 01:23:49 +00:00
SjLjEHPrepare.cpp ADT: Remove == and != comparisons between ilist iterators and pointers 2016-02-21 20:39:50 +00:00
SlotIndexes.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
SpillPlacement.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
SpillPlacement.h
Spiller.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
SplitKit.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
SplitKit.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
StackColoring.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
StackMapLivenessAnalysis.cpp [StackMap Liveness] Calling the base class' getAnalysisUsage method. NFCI. 2015-07-07 02:05:18 +00:00
StackMaps.cpp Move most user of TargetMachine::getDataLayout to the Module one 2015-07-16 06:11:10 +00:00
StackProtector.cpp [BPI] Replace weights by probabilities in BPI. 2015-12-22 18:56:14 +00:00
StackSlotColoring.cpp CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFC 2016-02-27 20:14:29 +00:00
TailDuplication.cpp Don't tail-duplicate blocks that contain convergent instructions. 2016-02-22 17:50:52 +00:00
TargetFrameLoweringImpl.cpp HHVM calling conventions. 2015-09-29 22:09:16 +00:00
TargetInstrInfo.cpp CodeGen: Change MachineInstr to use MachineInstr&, NFC 2016-02-27 20:01:33 +00:00
TargetLoweringBase.cpp [Power PC] softening long double type 2016-02-04 14:43:50 +00:00
TargetLoweringObjectFileImpl.cpp Add prefix based function layout when profile is available. 2016-02-23 03:39:24 +00:00
TargetOptionsImpl.cpp Use function attribute "trap-func-name" and remove TargetOptions::TrapFuncName. 2015-07-02 22:13:27 +00:00
TargetRegisterInfo.cpp raw_ostream: << operator for callables with raw_ostream argument 2015-12-04 01:31:59 +00:00
TargetSchedule.cpp CodeGen: TII: Take MachineInstr& in predicate API, NFC 2016-02-23 02:46:52 +00:00
TwoAddressInstructionPass.cpp CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFC 2016-02-27 20:14:29 +00:00
UnreachableBlockElim.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
VirtRegMap.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
WinEHPrepare.cpp [WinEH] Don't remove unannotated inline-asm calls 2016-02-26 00:04:25 +00:00
module.modulemap

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.