llvm-project/llvm/test/MC/Disassembler
Vladimir Medic 43e978234a This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.
llvm-svn: 202706
2014-03-03 13:12:59 +00:00
..
AArch64 [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction. 2013-11-29 01:29:16 +00:00
ARM ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions 2014-01-12 04:36:01 +00:00
Mips This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. 2014-03-03 13:12:59 +00:00
PowerPC Add a disassembler to the PowerPC backend 2013-12-19 16:13:01 +00:00
Sparc [Sparc] Add return/rett instruction to Sparc backend. 2014-03-02 22:55:53 +00:00
SystemZ [SystemZ] Add MC support for interlocked-access 1 instructions 2013-12-24 15:14:05 +00:00
X86 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 2014-02-19 05:34:21 +00:00
XCore [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00