llvm-project/mlir
aartbik 63b3933d0c [mlir] [VectorOps] Replace zero fma with mult for vector.contract
More efficient implementation of the multiply-reduce pair,
no need to add in a zero vector. Microbenchmarking on AVX2
yields the following difference in vector.contract speedup
(over strict-order scalar reduction).

SPEEDUP     SIMD-fma SIMD-mul
4x4	    1.45 	 2.00
8x8	    1.40 	 1.90
32x32    	5.32 	 5.80

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D82833
2020-06-30 09:04:20 -07:00
..
cmake/modules Install the MLIRTableGen static library. 2020-06-11 18:23:24 -07:00
docs [MLIR] Add variadic isa<> for Type, Value, and Attribute 2020-06-29 15:04:48 -07:00
examples [MLIR] Add variadic isa<> for Type, Value, and Attribute 2020-06-29 15:04:48 -07:00
include [ods] Update Operator to record Arg->[Attr|Operand]Index mapping 2020-06-29 16:40:52 -07:00
integration_test [mlir] [VectorOps] Extend vector reduction integration test with reassoc=true cases. 2020-06-29 13:28:20 -07:00
lib [mlir] [VectorOps] Replace zero fma with mult for vector.contract 2020-06-30 09:04:20 -07:00
test [mlir] [VectorOps] Replace zero fma with mult for vector.contract 2020-06-30 09:04:20 -07:00
tools [ods] Update Operator to record Arg->[Attr|Operand]Index mapping 2020-06-29 16:40:52 -07:00
unittests [mlir-tblgen] Use fully qualified names in generated code files 2020-06-26 15:05:33 +02:00
utils [MLIR][SPIRV] Extend automation script to generate coverage report. 2020-06-23 11:42:59 -04:00
.clang-format [mlir] add .clang-format 2019-03-29 12:41:43 -07:00
.clang-tidy Fix MLIR clang-tidy: when tweaking it does not inherit from the parent 2020-03-07 17:44:21 +00:00
CMakeLists.txt [mlir] [integration_test] Make integration tests default OFF 2020-06-15 14:33:18 -07:00
LICENSE.TXT Add the Apache2 with LLVM exceptions license to MLIR 2019-12-24 00:58:06 -08:00
README.md mlir README.md: Fix the syntax 2019-12-24 13:31:07 +01:00

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.