forked from OSchip/llvm-project
36 lines
953 B
TableGen
36 lines
953 B
TableGen
// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s -o - 2>%t
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// RUN: FileCheck %s < %t
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include "llvm/Target/Target.td"
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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class I<dag OOps, dag IOps, list<dag> Pat>
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: Instruction {
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let Namespace = "MyTarget";
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let OutOperandList = OOps;
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let InOperandList = IOps;
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let Pattern = Pat;
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bits<32> Inst;
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bits<32> SoftFail;
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}
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def A : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
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let Size = 4;
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let Inst{31...0} = 0;
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}
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def B : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
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let Size = 4;
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let Inst{31...0} = 0;
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}
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// CHECK: Decoding Conflict:
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// CHECK: 00000000000000000000000000000000
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// CHECK: ................................
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// CHECK: A 00000000000000000000000000000000
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// CHECK: B 00000000000000000000000000000000
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