forked from OSchip/llvm-project
42652c1d6e
* Prevent the generation of invalid shift instructions by constraining the immediate field. I've limited the shift field to constant values only, adding the `R_SPARC_5`/`R_SPARC_6` relocations is trivial if needed (but I can't really think of a use case for those). * Fix the generation of PC-relative `call` * Fix the transformation of `jmp sym` into `jmpl` * Emit fixups for simm13 operands I moved the choice of the correct relocation into the code emitter as I've seen the other backends do, it can be definitely cleaner but the aim was to reduce the scope of the patch as much as possible. Fixes the problems raised by joerg in L254199 Reviewed By: dcederman Differential Revision: https://reviews.llvm.org/D78193 |
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| .. | ||
| leon-instructions.s | ||
| leon-pwrpsr-instruction.s | ||
| lit.local.cfg | ||
| sparc-alu-instructions.s | ||
| sparc-asm-errors.s | ||
| sparc-assembly-exprs.s | ||
| sparc-atomic-instructions.s | ||
| sparc-coproc.s | ||
| sparc-ctrl-instructions.s | ||
| sparc-directive-xword.s | ||
| sparc-directives.s | ||
| sparc-fp-instructions.s | ||
| sparc-little-endian.s | ||
| sparc-mem-instructions.s | ||
| sparc-misc-instructions.s | ||
| sparc-nop-data.s | ||
| sparc-pic.s | ||
| sparc-relocations.s | ||
| sparc-special-registers.s | ||
| sparc-synthetic-instructions.s | ||
| sparc-tls-relocations.s | ||
| sparc-traps.s | ||
| sparc-v9-traps.s | ||
| sparc-vis.s | ||
| sparc64-alu-instructions.s | ||
| sparc64-ctrl-instructions.s | ||
| sparcv8-instructions.s | ||
| sparcv9-atomic-instructions.s | ||
| sparcv9-instructions.s | ||