llvm-project/llvm/lib/CodeGen
Jonas Paulsson e86327f290 [TwoAddressInstructionPass] Bugfix in handling of sunk instructions.
An instruction returned by TII->convertToThreeAddress() may contain a %noreg
(undef) operand, which is not expected by tryInstructionTransform(). So if
this MI is sunk to a lower point in MBB, it must be skipped when later
encountered.

A new set SunkInstrs is used for this purpose.

Note: there is no test supplied here, as this was triggered on SystemZ while
working on a review of instruction flags. A test case for this bugfix will be
included in the upcoming SystemZ commit.

Review: Quentin Colombet
https://reviews.llvm.org/D40711

llvm-svn: 319646
2017-12-04 10:03:14 +00:00
..
AsmPrinter Split TypeTableBuilder into two classes. 2017-11-30 18:39:50 +00:00
GlobalISel GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES 2017-12-01 08:19:10 +00:00
MIRParser [mir] Print/Parse both MOLoad and MOStore when they occur together. 2017-11-28 18:57:02 +00:00
SelectionDAG [DAGCombine] Remove isAndLoadExtLoad arguments 2017-12-04 09:48:26 +00:00
AggressiveAntiDepBreaker.cpp [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
AggressiveAntiDepBreaker.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AllocationOrder.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
AllocationOrder.h [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints. 2017-11-10 08:46:26 +00:00
Analysis.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AntiDepBreaker.h [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-09-29 21:55:49 +00:00
AtomicExpandPass.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
BasicTargetTransformInfo.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
BranchFolding.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
BranchFolding.h [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-10-10 22:33:29 +00:00
BranchRelaxation.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
BuiltinGCs.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
CMakeLists.txt [CodeGen] Separate MachineOperand implementation from MachineInstr 2017-11-28 17:58:43 +00:00
CalcSpillWeights.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
CallingConvLower.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
CodeGen.cpp Rename CountingFunctionInserter and use for both mcount and cygprofile calls, before and after inlining 2017-11-14 21:09:45 +00:00
CodeGenPrepare.cpp [CGP] Enable complex addr mode 2017-11-29 09:48:50 +00:00
CriticalAntiDepBreaker.cpp [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
CriticalAntiDepBreaker.h [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-09-29 21:55:49 +00:00
DFAPacketizer.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
DeadMachineInstructionElim.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
DetectDeadLanes.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
DwarfEHPrepare.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
EarlyIfConversion.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
EdgeBundles.cpp
ExecutionDepsFix.cpp [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
ExpandISelPseudos.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
ExpandMemCmp.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
ExpandPostRAPseudos.cpp [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
ExpandReductions.cpp [IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag 2017-11-06 16:27:15 +00:00
FEntryInserter.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
FaultMaps.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
FuncletLayout.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
GCMetadata.cpp [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-06-07 23:53:32 +00:00
GCMetadataPrinter.cpp [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-06-07 23:53:32 +00:00
GCRootLowering.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
GCStrategy.cpp
GlobalMerge.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
IfConversion.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
ImplicitNullChecks.cpp Mark all library options as hidden. 2017-12-01 00:53:10 +00:00
InlineSpiller.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
InterferenceCache.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
InterferenceCache.h [CodeGen] Fix build bots which uses old Clang broken in r314046. (NFC) 2017-09-22 23:55:32 +00:00
InterleavedAccessPass.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
IntrinsicLowering.cpp Support generic lowering of vector bswap 2017-11-30 11:06:22 +00:00
LLVMBuild.txt LLVMCodeGen: Add ProfileData into deps corresponding to r300277. 2017-04-14 00:36:06 +00:00
LLVMTargetMachine.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LatencyPriorityQueue.cpp Assert correct removal of SUnit in LatencyPriorityQueue 2017-11-16 10:18:07 +00:00
LazyMachineBlockFrequencyInfo.cpp
LexicalScopes.cpp Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people. 2017-10-15 14:32:27 +00:00
LiveDebugValues.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
LiveDebugVariables.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LiveDebugVariables.h [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-08-24 21:21:39 +00:00
LiveInterval.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
LiveIntervalAnalysis.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
LiveIntervalUnion.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
LivePhysRegs.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
LiveRangeCalc.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
LiveRangeCalc.h [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-08-24 21:21:39 +00:00
LiveRangeEdit.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
LiveRangeShrink.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LiveRangeUtils.h
LiveRegMatrix.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
LiveRegUnits.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LiveStackAnalysis.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LiveVariables.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
LocalStackSlotAllocation.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
LowLevelType.cpp [GlobalISel] Support vector-of-pointers in LLT 2017-04-19 07:23:57 +00:00
LowerEmuTLS.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MIRCanonicalizerPass.cpp Make helpers static. NFC. 2017-11-24 14:55:41 +00:00
MIRPrinter.cpp Mark all library options as hidden. 2017-12-01 00:53:10 +00:00
MIRPrintingPass.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
MachineBasicBlock.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
MachineBlockFrequencyInfo.cpp Irreducible loop metadata for more accurate block frequency under PGO. 2017-11-02 22:26:51 +00:00
MachineBlockPlacement.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MachineBranchProbabilityInfo.cpp
MachineCSE.cpp [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
MachineCombiner.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MachineCopyPropagation.cpp [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
MachineDominanceFrontier.cpp [Dominators] Make IsPostDominator a template parameter 2017-07-14 18:26:09 +00:00
MachineDominators.cpp Mark all library options as hidden. 2017-12-01 00:53:10 +00:00
MachineFrameInfo.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MachineFunction.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
MachineFunctionPass.cpp CodeGen: Refactor MIR parsing 2017-06-06 00:44:35 +00:00
MachineFunctionPrinterPass.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
MachineInstr.cpp [CodeGen] Separate MachineOperand implementation from MachineInstr 2017-11-28 17:58:43 +00:00
MachineInstrBundle.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MachineLICM.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MachineLoopInfo.cpp Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people. 2017-10-15 14:32:27 +00:00
MachineModuleInfo.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MachineModuleInfoImpls.cpp [MachineModuleInfoImpls] Replace qsort with array_pod_sort 2017-10-26 16:07:20 +00:00
MachineOperand.cpp CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT 2017-12-02 22:13:22 +00:00
MachineOptimizationRemarkEmitter.cpp [opt-remarks] If hotness threshold is set, ignore remarks without hotness 2017-12-01 20:41:38 +00:00
MachineOutliner.cpp [MachineOutliner] NFC: Throw out self-intersections on candidates early 2017-12-01 21:56:56 +00:00
MachinePassRegistry.cpp
MachinePipeliner.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MachinePostDominators.cpp [Dominators] Make IsPostDominator a template parameter 2017-07-14 18:26:09 +00:00
MachineRegionInfo.cpp Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people. 2017-10-15 14:32:27 +00:00
MachineRegisterInfo.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
MachineSSAUpdater.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
MachineScheduler.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
MachineSink.cpp [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
MachineTraceMetrics.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
MachineVerifier.cpp [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
MacroFusion.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
OptimizePHIs.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
PHIElimination.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
ParallelCG.cpp
PatchableFunction.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
PeepholeOptimizer.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
PostRAHazardRecognizer.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
PostRASchedulerList.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
PreISelIntrinsicLowering.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-09-13 21:15:20 +00:00
ProcessImplicitDefs.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
PrologEpilogInserter.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
PseudoSourceValue.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
README.txt [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
RegAllocBase.cpp Mark all library options as hidden. 2017-12-01 00:53:10 +00:00
RegAllocBase.h [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-09-13 21:15:20 +00:00
RegAllocBasic.cpp [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
RegAllocFast.cpp [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
RegAllocGreedy.cpp Mark all library options as hidden. 2017-12-01 00:53:10 +00:00
RegAllocPBQP.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
RegUsageInfoCollector.cpp [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
RegUsageInfoPropagate.cpp IPRA: Don't assume called function is first call operand 2017-08-24 07:55:15 +00:00
RegisterClassInfo.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
RegisterCoalescer.cpp Mark all library options as hidden. 2017-12-01 00:53:10 +00:00
RegisterCoalescer.h [CodeGen] Fix some Clang-tidy modernize-use-default-member-init and Include What You Use warnings; other minor fixes (NFC). 2017-09-22 23:46:57 +00:00
RegisterPressure.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
RegisterScavenging.cpp [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
RegisterUsageInfo.cpp [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
RenameIndependentSubregs.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
ResetMachineFunctionPass.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SafeStack.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
SafeStackColoring.cpp Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people. 2017-10-15 14:32:27 +00:00
SafeStackColoring.h [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-10-10 22:33:29 +00:00
SafeStackLayout.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-10-10 22:33:29 +00:00
SafeStackLayout.h [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-10-10 22:33:29 +00:00
ScalarizeMaskedMemIntrin.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
ScheduleDAG.cpp [CodeGen] Rename functions PrintReg* to printReg* 2017-11-28 12:42:37 +00:00
ScheduleDAGInstrs.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
ScheduleDAGPrinter.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
ScoreboardHazardRecognizer.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
ShadowStackGCLowering.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-09-13 21:15:20 +00:00
ShrinkWrap.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
SjLjEHPrepare.cpp [SjLj] Replace recursive block marking algorithm with iterative algorithm 2017-07-12 23:05:15 +00:00
SlotIndexes.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
SpillPlacement.cpp [CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What You Use warnings; other minor fixes (NFC). 2017-09-21 23:20:16 +00:00
SpillPlacement.h [CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What You Use warnings; other minor fixes (NFC). 2017-09-21 23:20:16 +00:00
Spiller.h [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-08-29 22:32:07 +00:00
SplitKit.cpp [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
SplitKit.h [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-08-29 22:32:07 +00:00
StackColoring.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
StackMapLivenessAnalysis.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
StackMaps.cpp Mark all library options as hidden. 2017-12-01 00:53:10 +00:00
StackProtector.cpp XOR the frame pointer with the stack cookie when protecting the stack 2017-11-30 22:41:21 +00:00
StackSlotColoring.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TailDuplication.cpp Add test case for r311511 2017-08-23 03:17:59 +00:00
TailDuplicator.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TargetFrameLoweringImpl.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TargetInstrInfo.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TargetLoweringBase.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TargetLoweringObjectFileImpl.cpp [COFF] Implement constructor priorities 2017-11-28 08:07:18 +00:00
TargetOptionsImpl.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TargetPassConfig.cpp Mark all library options as hidden. 2017-12-01 00:53:10 +00:00
TargetRegisterInfo.cpp [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
TargetSchedule.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TargetSubtargetInfo.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
TwoAddressInstructionPass.cpp [TwoAddressInstructionPass] Bugfix in handling of sunk instructions. 2017-12-04 10:03:14 +00:00
UnreachableBlockElim.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
VirtRegMap.cpp [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
WinEHPrepare.cpp Guard print() functions only used by dump() functions. 2017-07-31 10:07:49 +00:00
XRayInstrumentation.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %noreg, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.