forked from OSchip/llvm-project
b1e8714af9
Summary: This patch is the first step in reducing HW prefetcher instruction tag collisions in inner loops for Falkor. It adds a pass that annotates IR loads with metadata to indicate that they are known to be strided loads, and adds a target lowering hook that translates this metadata to a target-specific MachineMemOperand flag. A follow on change will use this MachineMemOperand flag to re-write instructions to reduce tag collisions. Reviewers: mcrosier, t.p.northover Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34963 llvm-svn: 308059 |
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| .. | ||
| atomic-memoperands.mir | ||
| cfi-def-cfa.mir | ||
| expected-target-flag-name.mir | ||
| generic-virtual-registers-error.mir | ||
| generic-virtual-registers-with-regbank-error.mir | ||
| intrinsics.mir | ||
| invalid-target-flag-name.mir | ||
| invalid-target-memoperands.mir | ||
| lit.local.cfg | ||
| multiple-lhs-operands.mir | ||
| register-operand-bank.mir | ||
| spill-fold.mir | ||
| stack-object-local-offset.mir | ||
| target-flags.mir | ||
| target-memoperands.mir | ||