forked from OSchip/llvm-project
112 lines
2.5 KiB
ArmAsm
112 lines
2.5 KiB
ArmAsm
// REQUIRES: arm
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// RUN: llvm-mc --triple=armv7a-none-eabi --arm-add-build-attributes -filetype=obj -o %t.o %s
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// RUN: ld.lld %t.o -o %t
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// RUN: llvm-objdump -d --no-show-raw-insn --triple=armv7a-none-eabi %t | FileCheck %s
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/// Test the short range cases of R_ARM_ALU_PC_G0. The range of the instruction
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/// depends on the number of trailing zeros of the displacement. In practice
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/// the maximum effective range will be 1024 bytes, which is a 4-byte aligned
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/// instruction to a 4-byte aligned word.
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.arm
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.section .os1, "ax", %progbits
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.balign 1024
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.word 0
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.word 0
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.word 0
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.word 0
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dat1:
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.word 0
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dat2:
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.word 0
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.section .os2, "ax", %progbits
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.balign 1024
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.global _start
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.type _start, %function
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_start:
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/// adr r0, dat1
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.inst 0xe24f0008
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.reloc 0, R_ARM_ALU_PC_G0, dat1
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/// adr r0, dat2
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.inst 0xe24f0008
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.reloc 4, R_ARM_ALU_PC_G0, dat2
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/// adr r0, dat3
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.inst 0xe24f0008
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.reloc 8, R_ARM_ALU_PC_G0, dat3
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/// adr r0, dat4
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.inst 0xe24f0008
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.reloc 0xc, R_ARM_ALU_PC_G0, dat4
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.section .os3, "ax", %progbits
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.balign 1024
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.word 0
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.word 0
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.word 0
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.word 0
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dat3:
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.word 0
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dat4:
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.word 0
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.section .os4, "ax", %progbits
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.thumb
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.type tfunc, %function
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tfunc:
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bx lr
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.section .os5, "ax", %progbits
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.arm
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.type arm_func, %function
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arm_func:
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.balign 4
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/// adr r0, tfunc
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.inst 0xe24f0008
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.reloc 0, R_ARM_ALU_PC_G0, tfunc
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/// adr r0, afunc
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.inst 0xe24f0008
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.reloc 4, R_ARM_ALU_PC_G0, afunc
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bx lr
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.section .os6, "ax", %progbits
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.type afunc, %function
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.balign 4
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afunc:
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bx lr
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// CHECK: 00020410 <dat1>:
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// CHECK-NEXT: 20410: andeq r0, r0, r0
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// CHECK: 00020414 <dat2>:
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// CHECK-NEXT: 20414: andeq r0, r0, r0
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// CHECK: 00020800 <_start>:
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/// 0x20800 + 0x8 - 0x3f8 = 0x11410 = dat1
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// CHECK-NEXT: 20800: sub r0, pc, #1016
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/// 0x20804 + 0x8 - 0x3f8 = 0x11414 = dat2
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// CHECK-NEXT: 20804: sub r0, pc, #1016
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/// 0x20808 + 0x8 + 0x400 = 0x11c10 = dat3
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// CHECK-NEXT: 20808: add r0, pc, #1024
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/// 0x2080c + 0x8 + 0x400 = 0x11c14 = dat4
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// CHECK-NEXT: 2080c: add r0, pc, #1024
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// CHECK: 00020c10 <dat3>:
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// CHECK-NEXT: 20c10: andeq r0, r0, r0
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// CHECK: 00020c14 <dat4>:
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// CHECK-NEXT: 20c14: andeq r0, r0, r0
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// CHECK: 00020c18 <tfunc>:
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// CHECK-NEXT: 20c18: bx lr
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// CHECK: 00020c1c <arm_func>:
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/// 0x20c1c + 0x8 - 0xb = 11c19 = tfunc
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// CHECK-NEXT: 20c1c: sub r0, pc, #11
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/// 0x20c20 + 0x8 = 0x11c28 = afunc
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// CHECK-NEXT: 20c20: add r0, pc, #0
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// CHECK-NEXT: 20c24: bx lr
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// CHECK: 00020c28 <afunc>:
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// CHECK-NEXT: 20c28: bx lr
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