Matt Arsenault 61738cbcb6 AMDGPU: Implement readcyclecounter ... This matches the behavior of the HSAIL clock instruction. s_realmemtime is used if the subtarget supports it, and falls back to s_memtime if not. Also introduces new intrinsics for each of s_memtime / s_memrealtime. llvm-svn: 262119		2016-02-27 08:53:46 +00:00
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AArch64	AArch64: remove CRC feature from Cyclone.	2016-02-24 18:10:17 +00:00
AMDGPU	AMDGPU: Implement readcyclecounter	2016-02-27 08:53:46 +00:00
ARM	ARM: disallow pc as a base register in Thumb2 memory ops.	2016-02-25 16:54:52 +00:00
AsmParser	[MC] Fixed parsing of macro arguments where expressions with spaces are present.	2016-02-11 13:48:49 +00:00
COFF	[codeview] Dump def range lengths in hex	2016-02-11 23:40:14 +00:00
Disassembler	Power9] Implement new vsx instructions: compare and conversion	2016-02-26 21:11:55 +00:00
ELF	Accept subtractions involving a weak symbol.	2016-01-20 18:57:48 +00:00
Hexagon	[Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding.	2016-02-16 20:38:17 +00:00
MachO	Form reform for MCDwarf.	2015-12-23 01:57:31 +00:00
Markup	…
Mips	[mips][microMIPS] Implement DINSU, DINSM, DINS instructions	2016-02-25 12:53:29 +00:00
PowerPC	Power9] Implement new vsx instructions: compare and conversion	2016-02-26 21:11:55 +00:00
Sparc	Reverting breaking change. Sorry.	2016-02-26 12:20:10 +00:00
SystemZ	[SystemZ] Sort relocs to avoid code corruption by linker optimization	2015-12-16 18:12:40 +00:00
X86	[X86] Move an encoding test from CodeGen to MC. NFC.	2016-02-26 23:00:03 +00:00