Simon Dardis 55e446737f [mips] Implement the 'dext' aliases and it's disassembly alias. ... The other members of the dext family of instructions (dextm, dextu) are traditionally handled by the assembler selecting the right variant of 'dext' depending on the values of the position and size operands. When these instructions are disassembled, rather than reporting the actual instruction, an equivalent aliased form of 'dext' is generated and is reported. This is to mimic the behaviour of binutils. Reviewers: slthakur, nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D34887 llvm-svn: 313276		2017-09-14 17:27:53 +00:00
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AArch64	[AArch64] v8.3-a complex number support	2017-08-31 09:27:04 +00:00
AMDGPU	[AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16	2017-08-16 15:16:32 +00:00
ARC	[ARC] Add ARC backend.	2017-08-24 15:40:33 +00:00
ARM	[ARM][AArch64] v8.3-A Javascript Conversion	2017-08-22 11:08:21 +00:00
Hexagon	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	[mips] Implement the 'dext' aliases and it's disassembly alias.	2017-09-14 17:27:53 +00:00
PowerPC	[Power9] Add missing instructions: extswsli, popcntb	2017-09-13 14:05:27 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Add support for IBM z14 processor (3/3)	2017-07-17 17:44:20 +00:00
X86	Revert "The current version of LLVM X86 disassembler incorrectly interprets some possible sets of x86 prefixes. This patch is the first step to close PR7709 and PR17697. There will be next patch(es) to close relative PRs." temporarily while some regressions are addressed.	2017-08-29 08:23:46 +00:00
XCore	…