llvm-project/llvm/test/CodeGen
Pablo Barrio 512f7ee315 [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations
Summary:
Expressions of the form x < 0 ? 0 :  x; and x < -1 ? -1 : x can be lowered using bit-operations instead of branching or conditional moves

In thumb-mode this results in a two-instruction sequence, a shift followed by a bic or or while in ARM/thumb2 mode that has flexible second operand the shift can be folded into a single bic/or instructions. In most cases this results in smaller code and possibly less branches, and in no case larger than before.

Patch by Martin Svanfeldt

Reviewers: fhahn, pbarrio, rogfer01

Reviewed By: pbarrio, rogfer01

Subscribers: chrib, yroux, eugenis, efriedma, rogfer01, aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D42574

llvm-svn: 326333
2018-02-28 17:13:07 +00:00
..
AArch64 Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
AMDGPU Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
ARC
ARM [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations 2018-02-28 17:13:07 +00:00
AVR [CodeGen] Unify the syntax of MBB successors in MIR and -debug output 2018-02-09 00:10:31 +00:00
BPF bpf: New codegen testcases for 32-bit subregister support 2018-02-23 23:49:33 +00:00
Generic [DebugInfo] Add remaining files to r325970 2018-02-23 23:13:18 +00:00
Hexagon [Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiply 2018-02-27 22:44:41 +00:00
Inputs
Lanai Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
MIR [GISel]: Verify COPIES involving generic registers. 2018-02-09 01:27:23 +00:00
MSP430 Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
Mips Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
NVPTX [DAGCombiner] Call ExtendUsesToFormExtLoad in (zext (and (load)))->(and (zextload)) even when the and does not have multiple uses 2018-02-15 20:20:32 +00:00
Nios2 [Nios2] Arithmetic instructions for R1 and R2 ISA. 2018-01-09 11:15:08 +00:00
PowerPC Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
RISCV [RISCV] Update two tests after r326208 2018-02-28 08:20:47 +00:00
SPARC Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
SystemZ Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
Thumb Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
Thumb2 ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR. 2018-02-27 19:00:59 +00:00
WebAssembly [WebAssembly] Add mechanisms for specifying an explicit import module name. 2018-02-09 23:13:22 +00:00
WinCFGuard Reland "Emit Function IDs table for Control Flow Guard" 2018-01-09 23:49:30 +00:00
WinEH
X86 [GlobalIsel][X86] Support G_INTTOPTR instruction. 2018-02-28 12:11:53 +00:00
XCore [XCore] Return true in enableMultipleCopyHints(). 2018-02-26 08:03:32 +00:00