forked from OSchip/llvm-project
229 lines
6.2 KiB
LLVM
229 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; then metadata checks MDn were added manually.
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; RUN: opt -passes='loop(unswitch),verify<loops>' -S < %s | FileCheck %s
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; RUN: opt -verify-memoryssa -passes='loop-mssa(unswitch),verify<loops>' -S < %s | FileCheck %s
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declare void @some_func()
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; Test for a trivially unswitchable switch with non-default case exiting.
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define i32 @test2(i32* %var, i32 %cond1, i32 %cond2) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 [[COND2:%.*]], label [[ENTRY_SPLIT:%.*]] [
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; CHECK-NEXT: i32 2, label [[LOOP_EXIT2:%.*]]
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; CHECK-NEXT: ], !prof ![[MD0:[0-9]+]]
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; CHECK: entry.split:
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; CHECK-NEXT: br label [[LOOP_BEGIN:%.*]]
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; CHECK: loop_begin:
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; CHECK-NEXT: [[VAR_VAL:%.*]] = load i32, i32* [[VAR:%.*]]
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; CHECK-NEXT: switch i32 [[COND2]], label [[LOOP2:%.*]] [
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; CHECK-NEXT: i32 0, label [[LOOP0:%.*]]
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; CHECK-NEXT: i32 1, label [[LOOP1:%.*]]
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; CHECK-NEXT: ], !prof ![[MD1:[0-9]+]]
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; CHECK: loop0:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]
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; CHECK: loop1:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop2:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop_latch:
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; CHECK-NEXT: br label [[LOOP_BEGIN]]
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; CHECK: loop_exit1:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit2:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit3:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop_begin
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loop_begin:
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%var_val = load i32, i32* %var
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switch i32 %cond2, label %loop2 [
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i32 0, label %loop0
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i32 1, label %loop1
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i32 2, label %loop_exit2
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], !prof !{!"branch_weights", i32 99, i32 100, i32 101, i32 102}
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loop0:
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call void @some_func()
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br label %loop_latch
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loop1:
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call void @some_func()
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br label %loop_latch
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loop2:
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call void @some_func()
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br label %loop_latch
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loop_latch:
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br label %loop_begin
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loop_exit1:
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ret i32 0
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loop_exit2:
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ret i32 0
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loop_exit3:
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ret i32 0
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}
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; Test for a trivially unswitchable switch with only the default case exiting.
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define i32 @test3(i32* %var, i32 %cond1, i32 %cond2) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 [[COND2:%.*]], label [[LOOP_EXIT2:%.*]] [
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; CHECK-NEXT: i32 0, label [[ENTRY_SPLIT:%.*]]
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; CHECK-NEXT: i32 1, label [[ENTRY_SPLIT]]
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; CHECK-NEXT: i32 2, label [[ENTRY_SPLIT]]
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; CHECK-NEXT: ], !prof ![[MD2:[0-9]+]]
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; CHECK: entry.split:
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; CHECK-NEXT: br label [[LOOP_BEGIN:%.*]]
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; CHECK: loop_begin:
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; CHECK-NEXT: [[VAR_VAL:%.*]] = load i32, i32* [[VAR:%.*]]
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; CHECK-NEXT: switch i32 [[COND2]], label [[LOOP2:%.*]] [
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; CHECK-NEXT: i32 0, label [[LOOP0:%.*]]
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; CHECK-NEXT: i32 1, label [[LOOP1:%.*]]
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; CHECK-NEXT: ], !prof ![[MD3:[0-9]+]]
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; CHECK: loop0:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]
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; CHECK: loop1:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop2:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop_latch:
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; CHECK-NEXT: br label [[LOOP_BEGIN]]
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; CHECK: loop_exit1:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit2:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit3:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop_begin
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loop_begin:
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%var_val = load i32, i32* %var
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switch i32 %cond2, label %loop_exit2 [
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i32 0, label %loop0
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i32 1, label %loop1
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i32 2, label %loop2
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], !prof !{!"branch_weights", i32 99, i32 100, i32 101, i32 102}
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loop0:
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call void @some_func()
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br label %loop_latch
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loop1:
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call void @some_func()
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br label %loop_latch
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loop2:
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call void @some_func()
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br label %loop_latch
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loop_latch:
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br label %loop_begin
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loop_exit1:
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ret i32 0
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loop_exit2:
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ret i32 0
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loop_exit3:
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ret i32 0
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}
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; Test for a trivially unswitchable switch with multiple exiting cases and
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; multiple looping cases.
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define i32 @test4(i32* %var, i32 %cond1, i32 %cond2) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 [[COND2:%.*]], label [[LOOP_EXIT2:%.*]] [
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; CHECK-NEXT: i32 13, label [[LOOP_EXIT1:%.*]]
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; CHECK-NEXT: i32 42, label [[LOOP_EXIT3:%.*]]
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; CHECK-NEXT: i32 0, label [[ENTRY_SPLIT:%.*]]
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; CHECK-NEXT: i32 1, label [[ENTRY_SPLIT]]
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; CHECK-NEXT: i32 2, label [[ENTRY_SPLIT]]
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; CHECK-NEXT: ], !prof ![[MD4:[0-9]+]]
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; CHECK: entry.split:
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; CHECK-NEXT: br label [[LOOP_BEGIN:%.*]]
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; CHECK: loop_begin:
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; CHECK-NEXT: [[VAR_VAL:%.*]] = load i32, i32* [[VAR:%.*]]
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; CHECK-NEXT: switch i32 [[COND2]], label [[LOOP2:%.*]] [
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; CHECK-NEXT: i32 0, label [[LOOP0:%.*]]
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; CHECK-NEXT: i32 1, label [[LOOP1:%.*]]
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; CHECK-NEXT: ], !prof ![[MD3:[0-9]+]]
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; CHECK: loop0:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]
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; CHECK: loop1:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop2:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop_latch:
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; CHECK-NEXT: br label [[LOOP_BEGIN]]
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; CHECK: loop_exit1:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit2:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit3:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop_begin
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loop_begin:
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%var_val = load i32, i32* %var
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switch i32 %cond2, label %loop_exit2 [
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i32 0, label %loop0
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i32 1, label %loop1
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i32 13, label %loop_exit1
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i32 2, label %loop2
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i32 42, label %loop_exit3
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], !prof !{!"branch_weights", i32 99, i32 100, i32 101, i32 113, i32 102, i32 142}
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loop0:
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call void @some_func()
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br label %loop_latch
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loop1:
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call void @some_func()
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br label %loop_latch
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loop2:
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call void @some_func()
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br label %loop_latch
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loop_latch:
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br label %loop_begin
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loop_exit1:
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ret i32 0
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loop_exit2:
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ret i32 0
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loop_exit3:
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ret i32 0
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}
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; CHECK: ![[MD0]] = !{!"branch_weights", i32 300, i32 102}
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; CHECK: ![[MD1]] = !{!"branch_weights", i32 99, i32 100, i32 101}
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; CHECK: ![[MD2]] = !{!"branch_weights", i32 99, i32 100, i32 101, i32 102}
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; CHECK: ![[MD3]] = !{!"branch_weights", i32 102, i32 100, i32 101}
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; CHECK: ![[MD4]] = !{!"branch_weights", i32 99, i32 113, i32 142, i32 100, i32 101, i32 102}
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