forked from OSchip/llvm-project
157 lines
5.1 KiB
LLVM
157 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define i1 @test1(i1 %a, i1 %b) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[A:%.*]]
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; CHECK-NEXT: ret i1 [[AND]]
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;
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%wc = call i1 @llvm.experimental.widenable.condition()
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%lhs = and i1 %b, %wc
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%and = and i1 %lhs, %a
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ret i1 %and
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}
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; Negative test - profitability of dropping WC from first use unclear
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define i1 @test1b(i1 %a, i1 %b) {
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; CHECK-LABEL: @test1b(
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; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]]
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; CHECK-NEXT: call void @use(i1 [[LHS]])
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[A:%.*]]
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; CHECK-NEXT: ret i1 [[AND]]
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;
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%wc = call i1 @llvm.experimental.widenable.condition()
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%lhs = and i1 %b, %wc
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call void @use(i1 %lhs)
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%and = and i1 %lhs, %a
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ret i1 %and
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}
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; multiple uses of A, B, WC doesn't change result
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define i1 @test1c(i1 %a, i1 %b) {
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; CHECK-LABEL: @test1c(
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; CHECK-NEXT: call void @use(i1 [[A:%.*]])
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; CHECK-NEXT: call void @use(i1 [[B:%.*]])
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; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: call void @use(i1 [[WC]])
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; CHECK-NEXT: [[LHS:%.*]] = and i1 [[WC]], [[B]]
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[A]]
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; CHECK-NEXT: ret i1 [[AND]]
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;
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call void @use(i1 %a)
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call void @use(i1 %b)
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%wc = call i1 @llvm.experimental.widenable.condition()
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call void @use(i1 %wc)
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%lhs = and i1 %b, %wc
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%and = and i1 %lhs, %a
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ret i1 %and
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}
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define i1 @test2(i1 %a, i1 %b) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: [[LHS:%.*]] = and i1 [[WC]], [[B:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[A:%.*]]
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; CHECK-NEXT: ret i1 [[AND]]
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;
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%wc = call i1 @llvm.experimental.widenable.condition()
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%lhs = and i1 %wc, %b
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%and = and i1 %lhs, %a
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ret i1 %and
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}
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; To test the rhs side, an instruction on lhs to prevent complexity
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; canonicalization reducing to above.
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define i1 @test3(i1 %a, i1 %b, i1 %c) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: [[LHS:%.*]] = and i1 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[RHS:%.*]] = and i1 [[WC]], [[C:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[RHS]]
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; CHECK-NEXT: ret i1 [[AND]]
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;
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%wc = call i1 @llvm.experimental.widenable.condition()
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%lhs = and i1 %a, %b
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%rhs = and i1 %c, %wc
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%and = and i1 %lhs, %rhs
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ret i1 %and
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}
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define i1 @test4(i1 %a, i1 %b, i1 %c) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: [[LHS:%.*]] = and i1 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[RHS:%.*]] = and i1 [[WC]], [[C:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[LHS]], [[RHS]]
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; CHECK-NEXT: ret i1 [[AND]]
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;
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%wc = call i1 @llvm.experimental.widenable.condition()
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%lhs = and i1 %a, %b
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%rhs = and i1 %wc, %c
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%and = and i1 %lhs, %rhs
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ret i1 %and
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}
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define i1 @test5(i1 %a, i1 %b) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: ret i1 [[WC]]
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;
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%wc = call i1 @llvm.experimental.widenable.condition()
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%and = and i1 %wc, %wc
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ret i1 %and
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}
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define i1 @test6(i1 %a, i1 %b) {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[WC]], [[WC2]]
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; CHECK-NEXT: ret i1 [[AND]]
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;
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%wc = call i1 @llvm.experimental.widenable.condition()
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%wc2 = call i1 @llvm.experimental.widenable.condition()
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%and = and i1 %wc, %wc2
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ret i1 %and
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}
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define i1 @test7(i1 %a, i1 %b) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: call void @use(i1 [[WC]])
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; CHECK-NEXT: [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[WC]], [[WC2]]
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; CHECK-NEXT: ret i1 [[AND]]
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;
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%wc = call i1 @llvm.experimental.widenable.condition()
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call void @use(i1 %wc)
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%wc2 = call i1 @llvm.experimental.widenable.condition()
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%and = and i1 %wc, %wc2
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ret i1 %and
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}
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define i1 @test8(i1 %a, i1 %b) {
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; CHECK-LABEL: @test8(
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; CHECK-NEXT: [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: [[WC2:%.*]] = call i1 @llvm.experimental.widenable.condition()
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; CHECK-NEXT: call void @use(i1 [[WC2]])
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[WC]], [[WC2]]
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; CHECK-NEXT: ret i1 [[AND]]
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;
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%wc = call i1 @llvm.experimental.widenable.condition()
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%wc2 = call i1 @llvm.experimental.widenable.condition()
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call void @use(i1 %wc2)
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%and = and i1 %wc, %wc2
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ret i1 %and
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}
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declare void @use(i1)
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declare i1 @llvm.experimental.widenable.condition()
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