forked from OSchip/llvm-project
7108b2dec1
This marks FSIN and other operations to EXPAND for scalable vectors, so that they are not assumed to be legal by the cost-model. Depends on D97470 Reviewed By: dmgreen, paulwalker-arm Differential Revision: https://reviews.llvm.org/D97471 |
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AArch64 | ||
AMDGPU | ||
ARM | ||
PowerPC | ||
RISCV | ||
SystemZ | ||
X86 | ||
free-intrinsics-datalayout.ll | ||
free-intrinsics-no_info.ll | ||
no_info.ll |