forked from OSchip/llvm-project
172 lines
5.5 KiB
LLVM
172 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; fold (urem undef, x) -> 0
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define <4 x i32> @combine_vec_urem_undef0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_urem_undef0:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_urem_undef0:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = urem <4 x i32> undef, %x
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ret <4 x i32> %1
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}
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; fold (urem x, undef) -> undef
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define <4 x i32> @combine_vec_urem_undef1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_urem_undef1:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_urem_undef1:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = urem <4 x i32> %x, undef
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ret <4 x i32> %1
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}
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; fold (urem x, pow2) -> (and x, (pow2-1))
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define <4 x i32> @combine_vec_urem_by_pow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_urem_by_pow2a:
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; SSE: # BB#0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_urem_by_pow2a:
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; AVX: # BB#0:
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; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = urem <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_urem_by_pow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_urem_by_pow2b:
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; SSE: # BB#0:
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; SSE-NEXT: pextrd $3, %xmm0, %eax
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; SSE-NEXT: andl $15, %eax
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; SSE-NEXT: movd %eax, %xmm1
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; SSE-NEXT: pextrd $2, %xmm0, %eax
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; SSE-NEXT: andl $7, %eax
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; SSE-NEXT: movd %eax, %xmm2
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; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
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; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,1,0,1]
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: andl $3, %eax
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; SSE-NEXT: movd %eax, %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,2,3]
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; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_urem_by_pow2b:
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; AVX: # BB#0:
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; AVX-NEXT: vpextrd $3, %xmm0, %eax
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; AVX-NEXT: andl $15, %eax
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; AVX-NEXT: vmovd %eax, %xmm1
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; AVX-NEXT: vpextrd $2, %xmm0, %eax
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; AVX-NEXT: andl $7, %eax
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; AVX-NEXT: vmovd %eax, %xmm2
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; AVX-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
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; AVX-NEXT: vpbroadcastq %xmm1, %xmm1
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; AVX-NEXT: vpextrd $1, %xmm0, %eax
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; AVX-NEXT: andl $3, %eax
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; AVX-NEXT: vmovd %eax, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,2,3]
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; AVX-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX-NEXT: retq
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%1 = urem <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
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ret <4 x i32> %1
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}
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; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
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define <4 x i32> @combine_vec_urem_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_urem_by_shl_pow2a:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $23, %xmm1
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE-NEXT: pslld $2, %xmm1
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; SSE-NEXT: pcmpeqd %xmm2, %xmm2
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; SSE-NEXT: paddd %xmm1, %xmm2
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_urem_by_shl_pow2a:
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; AVX: # BB#0:
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; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2
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; AVX-NEXT: vpsllvd %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y
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%2 = urem <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_urem_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_urem_by_shl_pow2b:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $23, %xmm1
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: cvttps2dq %xmm1, %xmm2
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm2
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: pextrd $1, %xmm2, %ecx
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: movl %edx, %ecx
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; SSE-NEXT: movd %xmm0, %eax
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; SSE-NEXT: movd %xmm2, %esi
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %esi
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; SSE-NEXT: movd %edx, %xmm1
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; SSE-NEXT: pinsrd $1, %ecx, %xmm1
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; SSE-NEXT: pextrd $2, %xmm0, %eax
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; SSE-NEXT: pextrd $2, %xmm2, %ecx
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: pinsrd $2, %edx, %xmm1
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; SSE-NEXT: pextrd $3, %xmm0, %eax
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; SSE-NEXT: pextrd $3, %xmm2, %ecx
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: pinsrd $3, %edx, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_urem_by_shl_pow2b:
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; AVX: # BB#0:
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; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [1,4,8,16]
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; AVX-NEXT: vpsllvd %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpextrd $1, %xmm1, %ecx
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; AVX-NEXT: vpextrd $1, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %ecx
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; AVX-NEXT: movl %edx, %ecx
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; AVX-NEXT: vmovd %xmm1, %esi
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; AVX-NEXT: vmovd %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %esi
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; AVX-NEXT: vmovd %edx, %xmm2
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; AVX-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
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; AVX-NEXT: vpextrd $2, %xmm1, %ecx
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; AVX-NEXT: vpextrd $2, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %ecx
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; AVX-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
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; AVX-NEXT: vpextrd $3, %xmm1, %ecx
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; AVX-NEXT: vpextrd $3, %xmm0, %eax
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; AVX-NEXT: xorl %edx, %edx
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; AVX-NEXT: divl %ecx
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; AVX-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> <i32 1, i32 4, i32 8, i32 16>, %y
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%2 = urem <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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