forked from OSchip/llvm-project
aaaeac6166
Field NumMicroOpcodes is currently used by mca to model the number of uOPs dispatched from the uOp-Queue to the out of order backend. From a 'dispatch' point of view, an instruction with zero opcodes is still valid; it simply doesn't consume any dispatch group slots. However, mca doesn't expect an instruction with zero uOPs to consume pipeline resources because it is seen as a contradiction. In practice, it only makes sense if such an instruction is eliminated and never really executed. It may be that mca is being too conservative here. However I believe that mca is right, and we should probably check that inconsistency in CodeGenSchedule.cpp (when we also verify scheduling classes in general). This patch removes the check for MayLoad and MayStore in mca. That check is probably too conservative: we are already checking if a zero-uops instruction consumes any processor resources. Note also that instructions with unmodelled side-effects also tend to set the MayLoad/MayStore flags even if - theoretically speaking - they might not even consume any hw resources in practice. In future we may want to implement different checks (possibly outside of mca) and potentially revisit the logic in mca that verifies instructions. For that reason I have raised PR44797. |
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| .. | ||
| HardwareUnits | ||
| Stages | ||
| CMakeLists.txt | ||
| CodeEmitter.cpp | ||
| Context.cpp | ||
| HWEventListener.cpp | ||
| InstrBuilder.cpp | ||
| Instruction.cpp | ||
| LLVMBuild.txt | ||
| Pipeline.cpp | ||
| Support.cpp | ||