llvm-project/llvm/test/CodeGen
Roman Tereshin 12a4dc4c34 [MIRParser] Accept overloaded intrinsic names w/o type suffixes
Function::lookupIntrinsicID is somewhat forgiving as it comes to
overloaded intrinsics' names: it returns an ID as soon as the name
provided has a prefix that matches a registered intrinsic's name w/o
actually checking that the rest of the name encodes all the concrete arg
types, let alone that those types are compatible with the intrinsic's
definition.

That's probably fine and comes in handy in MIR serialization: we don't
care about IR types at MIR level and every intrinsic should be
selectable based on its ID and low-level types (LLTs) of its operands,
including the overloaded ones, so there is no point in serializing
mangled IR types as part of the intrinsic's name.

However, lookupIntrinsicID is somewhat inconsistent in its forgiveness:
if the name provided is actually an exact match, it will refuse to
return the ID if the intrinsic is overloaded. There is probably no
real reason for that and it renders MIRParser incapable to deserialize
MIR MIRPrinter serialized.

This commit fixes it.

Reviewers: rnk, aditya_nandakumar, qcolombet, thegameg, dsanders,
marcello.maggioni

Reviewed By: bogner

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D43267

llvm-svn: 326387
2018-02-28 23:51:49 +00:00
..
AArch64 [TLS] use emulated TLS if the target supports only this mode 2018-02-28 17:48:55 +00:00
AMDGPU [AMDGPU] added writelane intrinsic 2018-02-28 19:10:32 +00:00
ARC
ARM [TLS] use emulated TLS if the target supports only this mode 2018-02-28 17:48:55 +00:00
AVR [CodeGen] Unify the syntax of MBB successors in MIR and -debug output 2018-02-09 00:10:31 +00:00
BPF bpf: New codegen testcases for 32-bit subregister support 2018-02-23 23:49:33 +00:00
Generic [DebugInfo] Add remaining files to r325970 2018-02-23 23:13:18 +00:00
Hexagon [Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiply 2018-02-27 22:44:41 +00:00
Inputs
Lanai Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
MIR [MIRParser] Accept overloaded intrinsic names w/o type suffixes 2018-02-28 23:51:49 +00:00
MSP430 Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
Mips [TLS] use emulated TLS if the target supports only this mode 2018-02-28 17:48:55 +00:00
NVPTX [DAGCombiner] Call ExtendUsesToFormExtLoad in (zext (and (load)))->(and (zextload)) even when the and does not have multiple uses 2018-02-15 20:20:32 +00:00
Nios2 [Nios2] Arithmetic instructions for R1 and R2 ISA. 2018-01-09 11:15:08 +00:00
PowerPC [TLS] use emulated TLS if the target supports only this mode 2018-02-28 17:48:55 +00:00
RISCV [RISCV] Update two tests after r326208 2018-02-28 08:20:47 +00:00
SPARC Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
SystemZ Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
Thumb Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
Thumb2 ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR. 2018-02-27 19:00:59 +00:00
WebAssembly [WebAssembly] Add mechanisms for specifying an explicit import module name. 2018-02-09 23:13:22 +00:00
WinCFGuard Reland "Emit Function IDs table for Control Flow Guard" 2018-01-09 23:49:30 +00:00
WinEH
X86 [X86] Regenerate cmpxchg tests 2018-02-28 22:57:23 +00:00
XCore [XCore] Return true in enableMultipleCopyHints(). 2018-02-26 08:03:32 +00:00