forked from OSchip/llvm-project
651 lines
22 KiB
TableGen
651 lines
22 KiB
TableGen
//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// InstrSchedModel annotations for out-of-order CPUs.
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//
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// These annotations are independent of the itinerary classes defined below.
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// Instructions with folded loads need to read the memory operand immediately,
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// but other register operands don't have to be read until the load is ready.
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// These operands are marked with ReadAfterLd.
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def ReadAfterLd : SchedRead;
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// Instructions with both a load and a store folded are modeled as a folded
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// load + WriteRMW.
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def WriteRMW : SchedWrite;
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// Most instructions can fold loads, so almost every SchedWrite comes in two
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// variants: With and without a folded load.
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// An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite
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// with a folded load.
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class X86FoldableSchedWrite : SchedWrite {
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// The SchedWrite to use when a load is folded into the instruction.
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SchedWrite Folded;
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}
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// Multiclass that produces a linked pair of SchedWrites.
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multiclass X86SchedWritePair {
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// Register-Memory operation.
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def Ld : SchedWrite;
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// Register-Register operation.
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def NAME : X86FoldableSchedWrite {
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let Folded = !cast<SchedWrite>(NAME#"Ld");
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}
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}
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// Arithmetic.
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defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
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defm WriteIMul : X86SchedWritePair; // Integer multiplication.
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def WriteIMulH : SchedWrite; // Integer multiplication, high part.
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defm WriteIDiv : X86SchedWritePair; // Integer division.
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def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
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// Integer shifts and rotates.
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defm WriteShift : X86SchedWritePair;
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// Loads, stores, and moves, not folded with other operations.
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def WriteLoad : SchedWrite;
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def WriteStore : SchedWrite;
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def WriteMove : SchedWrite;
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// Idioms that clear a register, like xorps %xmm0, %xmm0.
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// These can often bypass execution ports completely.
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def WriteZero : SchedWrite;
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// Branches don't produce values, so they have no latency, but they still
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// consume resources. Indirect branches can fold loads.
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defm WriteJump : X86SchedWritePair;
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// Floating point. This covers both scalar and vector operations.
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defm WriteFAdd : X86SchedWritePair; // Floating point add/sub/compare.
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defm WriteFMul : X86SchedWritePair; // Floating point multiplication.
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defm WriteFDiv : X86SchedWritePair; // Floating point division.
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defm WriteFSqrt : X86SchedWritePair; // Floating point square root.
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defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal estimate.
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defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate.
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defm WriteFMA : X86SchedWritePair; // Fused Multiply Add.
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defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles.
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defm WriteFBlend : X86SchedWritePair; // Floating point vector blends.
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defm WriteFVarBlend : X86SchedWritePair; // Fp vector variable blends.
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// FMA Scheduling helper class.
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class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
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// Vector integer operations.
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defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals.
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defm WriteVecShift : X86SchedWritePair; // Vector integer shifts.
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defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply.
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defm WriteShuffle : X86SchedWritePair; // Vector shuffles.
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defm WriteBlend : X86SchedWritePair; // Vector blends.
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defm WriteVarBlend : X86SchedWritePair; // Vector variable blends.
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defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
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// Vector bitwise operations.
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// These are often used on both floating point and integer vectors.
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defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor.
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// Conversion between integer and float.
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defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer.
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defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float.
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defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion.
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// Strings instructions.
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// Packed Compare Implicit Length Strings, Return Mask
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defm WritePCmpIStrM : X86SchedWritePair;
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// Packed Compare Explicit Length Strings, Return Mask
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defm WritePCmpEStrM : X86SchedWritePair;
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// Packed Compare Implicit Length Strings, Return Index
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defm WritePCmpIStrI : X86SchedWritePair;
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// Packed Compare Explicit Length Strings, Return Index
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defm WritePCmpEStrI : X86SchedWritePair;
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// AES instructions.
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defm WriteAESDecEnc : X86SchedWritePair; // Decryption, encryption.
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defm WriteAESIMC : X86SchedWritePair; // InvMixColumn.
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defm WriteAESKeyGen : X86SchedWritePair; // Key Generation.
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// Carry-less multiplication instructions.
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defm WriteCLMul : X86SchedWritePair;
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// Catch-all for expensive system instructions.
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def WriteSystem : SchedWrite;
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// AVX2.
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defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles.
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defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles.
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defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts.
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// Old microcoded instructions that nobody use.
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def WriteMicrocoded : SchedWrite;
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// Fence instructions.
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def WriteFence : SchedWrite;
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// Nop, not very useful expect it provides a model for nops!
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def WriteNop : SchedWrite;
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for X86
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def IIC_ALU_MEM : InstrItinClass;
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def IIC_ALU_NONMEM : InstrItinClass;
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def IIC_LEA : InstrItinClass;
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def IIC_LEA_16 : InstrItinClass;
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def IIC_MUL8 : InstrItinClass;
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def IIC_MUL16_MEM : InstrItinClass;
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def IIC_MUL16_REG : InstrItinClass;
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def IIC_MUL32_MEM : InstrItinClass;
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def IIC_MUL32_REG : InstrItinClass;
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def IIC_MUL64 : InstrItinClass;
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// imul by al, ax, eax, tax
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def IIC_IMUL8 : InstrItinClass;
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def IIC_IMUL16_MEM : InstrItinClass;
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def IIC_IMUL16_REG : InstrItinClass;
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def IIC_IMUL32_MEM : InstrItinClass;
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def IIC_IMUL32_REG : InstrItinClass;
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def IIC_IMUL64 : InstrItinClass;
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// imul reg by reg|mem
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def IIC_IMUL16_RM : InstrItinClass;
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def IIC_IMUL16_RR : InstrItinClass;
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def IIC_IMUL32_RM : InstrItinClass;
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def IIC_IMUL32_RR : InstrItinClass;
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def IIC_IMUL64_RM : InstrItinClass;
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def IIC_IMUL64_RR : InstrItinClass;
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// imul reg = reg/mem * imm
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def IIC_IMUL16_RMI : InstrItinClass;
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def IIC_IMUL16_RRI : InstrItinClass;
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def IIC_IMUL32_RMI : InstrItinClass;
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def IIC_IMUL32_RRI : InstrItinClass;
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def IIC_IMUL64_RMI : InstrItinClass;
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def IIC_IMUL64_RRI : InstrItinClass;
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// div
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def IIC_DIV8_MEM : InstrItinClass;
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def IIC_DIV8_REG : InstrItinClass;
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def IIC_DIV16 : InstrItinClass;
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def IIC_DIV32 : InstrItinClass;
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def IIC_DIV64 : InstrItinClass;
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// idiv
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def IIC_IDIV8 : InstrItinClass;
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def IIC_IDIV16 : InstrItinClass;
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def IIC_IDIV32 : InstrItinClass;
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def IIC_IDIV64 : InstrItinClass;
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// neg/not/inc/dec
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def IIC_UNARY_REG : InstrItinClass;
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def IIC_UNARY_MEM : InstrItinClass;
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// add/sub/and/or/xor/sbc/cmp/test
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def IIC_BIN_MEM : InstrItinClass;
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def IIC_BIN_NONMEM : InstrItinClass;
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// adc/sbc
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def IIC_BIN_CARRY_MEM : InstrItinClass;
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def IIC_BIN_CARRY_NONMEM : InstrItinClass;
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// shift/rotate
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def IIC_SR : InstrItinClass;
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// shift double
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def IIC_SHD16_REG_IM : InstrItinClass;
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def IIC_SHD16_REG_CL : InstrItinClass;
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def IIC_SHD16_MEM_IM : InstrItinClass;
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def IIC_SHD16_MEM_CL : InstrItinClass;
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def IIC_SHD32_REG_IM : InstrItinClass;
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def IIC_SHD32_REG_CL : InstrItinClass;
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def IIC_SHD32_MEM_IM : InstrItinClass;
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def IIC_SHD32_MEM_CL : InstrItinClass;
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def IIC_SHD64_REG_IM : InstrItinClass;
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def IIC_SHD64_REG_CL : InstrItinClass;
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def IIC_SHD64_MEM_IM : InstrItinClass;
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def IIC_SHD64_MEM_CL : InstrItinClass;
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// cmov
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def IIC_CMOV16_RM : InstrItinClass;
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def IIC_CMOV16_RR : InstrItinClass;
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def IIC_CMOV32_RM : InstrItinClass;
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def IIC_CMOV32_RR : InstrItinClass;
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def IIC_CMOV64_RM : InstrItinClass;
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def IIC_CMOV64_RR : InstrItinClass;
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// set
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def IIC_SET_R : InstrItinClass;
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def IIC_SET_M : InstrItinClass;
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// jmp/jcc/jcxz
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def IIC_Jcc : InstrItinClass;
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def IIC_JCXZ : InstrItinClass;
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def IIC_JMP_REL : InstrItinClass;
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def IIC_JMP_REG : InstrItinClass;
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def IIC_JMP_MEM : InstrItinClass;
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def IIC_JMP_FAR_MEM : InstrItinClass;
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def IIC_JMP_FAR_PTR : InstrItinClass;
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// loop
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def IIC_LOOP : InstrItinClass;
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def IIC_LOOPE : InstrItinClass;
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def IIC_LOOPNE : InstrItinClass;
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// call
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def IIC_CALL_RI : InstrItinClass;
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def IIC_CALL_MEM : InstrItinClass;
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def IIC_CALL_FAR_MEM : InstrItinClass;
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def IIC_CALL_FAR_PTR : InstrItinClass;
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// ret
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def IIC_RET : InstrItinClass;
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def IIC_RET_IMM : InstrItinClass;
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//sign extension movs
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def IIC_MOVSX : InstrItinClass;
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def IIC_MOVSX_R16_R8 : InstrItinClass;
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def IIC_MOVSX_R16_M8 : InstrItinClass;
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def IIC_MOVSX_R16_R16 : InstrItinClass;
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def IIC_MOVSX_R32_R32 : InstrItinClass;
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//zero extension movs
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def IIC_MOVZX : InstrItinClass;
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def IIC_MOVZX_R16_R8 : InstrItinClass;
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def IIC_MOVZX_R16_M8 : InstrItinClass;
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def IIC_REP_MOVS : InstrItinClass;
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def IIC_REP_STOS : InstrItinClass;
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// SSE scalar/parallel binary operations
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def IIC_SSE_ALU_F32S_RR : InstrItinClass;
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def IIC_SSE_ALU_F32S_RM : InstrItinClass;
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def IIC_SSE_ALU_F64S_RR : InstrItinClass;
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def IIC_SSE_ALU_F64S_RM : InstrItinClass;
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def IIC_SSE_MUL_F32S_RR : InstrItinClass;
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def IIC_SSE_MUL_F32S_RM : InstrItinClass;
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def IIC_SSE_MUL_F64S_RR : InstrItinClass;
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def IIC_SSE_MUL_F64S_RM : InstrItinClass;
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def IIC_SSE_DIV_F32S_RR : InstrItinClass;
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def IIC_SSE_DIV_F32S_RM : InstrItinClass;
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def IIC_SSE_DIV_F64S_RR : InstrItinClass;
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def IIC_SSE_DIV_F64S_RM : InstrItinClass;
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def IIC_SSE_ALU_F32P_RR : InstrItinClass;
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def IIC_SSE_ALU_F32P_RM : InstrItinClass;
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def IIC_SSE_ALU_F64P_RR : InstrItinClass;
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def IIC_SSE_ALU_F64P_RM : InstrItinClass;
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def IIC_SSE_MUL_F32P_RR : InstrItinClass;
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def IIC_SSE_MUL_F32P_RM : InstrItinClass;
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def IIC_SSE_MUL_F64P_RR : InstrItinClass;
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def IIC_SSE_MUL_F64P_RM : InstrItinClass;
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def IIC_SSE_DIV_F32P_RR : InstrItinClass;
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def IIC_SSE_DIV_F32P_RM : InstrItinClass;
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def IIC_SSE_DIV_F64P_RR : InstrItinClass;
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def IIC_SSE_DIV_F64P_RM : InstrItinClass;
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def IIC_SSE_COMIS_RR : InstrItinClass;
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def IIC_SSE_COMIS_RM : InstrItinClass;
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def IIC_SSE_HADDSUB_RR : InstrItinClass;
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def IIC_SSE_HADDSUB_RM : InstrItinClass;
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def IIC_SSE_BIT_P_RR : InstrItinClass;
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def IIC_SSE_BIT_P_RM : InstrItinClass;
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def IIC_SSE_INTALU_P_RR : InstrItinClass;
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def IIC_SSE_INTALU_P_RM : InstrItinClass;
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def IIC_SSE_INTALUQ_P_RR : InstrItinClass;
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def IIC_SSE_INTALUQ_P_RM : InstrItinClass;
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def IIC_SSE_INTMUL_P_RR : InstrItinClass;
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def IIC_SSE_INTMUL_P_RM : InstrItinClass;
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def IIC_SSE_INTSH_P_RR : InstrItinClass;
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def IIC_SSE_INTSH_P_RM : InstrItinClass;
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def IIC_SSE_INTSH_P_RI : InstrItinClass;
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def IIC_SSE_INTSHDQ_P_RI : InstrItinClass;
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def IIC_SSE_SHUFP : InstrItinClass;
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def IIC_SSE_PSHUF_RI : InstrItinClass;
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def IIC_SSE_PSHUF_MI : InstrItinClass;
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def IIC_SSE_UNPCK : InstrItinClass;
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def IIC_SSE_MOVMSK : InstrItinClass;
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def IIC_SSE_MASKMOV : InstrItinClass;
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def IIC_SSE_PEXTRW : InstrItinClass;
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def IIC_SSE_PINSRW : InstrItinClass;
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def IIC_SSE_PABS_RR : InstrItinClass;
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def IIC_SSE_PABS_RM : InstrItinClass;
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def IIC_SSE_SQRTPS_RR : InstrItinClass;
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def IIC_SSE_SQRTPS_RM : InstrItinClass;
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def IIC_SSE_SQRTSS_RR : InstrItinClass;
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def IIC_SSE_SQRTSS_RM : InstrItinClass;
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def IIC_SSE_SQRTPD_RR : InstrItinClass;
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def IIC_SSE_SQRTPD_RM : InstrItinClass;
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def IIC_SSE_SQRTSD_RR : InstrItinClass;
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def IIC_SSE_SQRTSD_RM : InstrItinClass;
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def IIC_SSE_RSQRTPS_RR : InstrItinClass;
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def IIC_SSE_RSQRTPS_RM : InstrItinClass;
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def IIC_SSE_RSQRTSS_RR : InstrItinClass;
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def IIC_SSE_RSQRTSS_RM : InstrItinClass;
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def IIC_SSE_RCPP_RR : InstrItinClass;
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def IIC_SSE_RCPP_RM : InstrItinClass;
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def IIC_SSE_RCPS_RR : InstrItinClass;
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def IIC_SSE_RCPS_RM : InstrItinClass;
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def IIC_SSE_MOV_S_RR : InstrItinClass;
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def IIC_SSE_MOV_S_RM : InstrItinClass;
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def IIC_SSE_MOV_S_MR : InstrItinClass;
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def IIC_SSE_MOVA_P_RR : InstrItinClass;
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def IIC_SSE_MOVA_P_RM : InstrItinClass;
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def IIC_SSE_MOVA_P_MR : InstrItinClass;
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def IIC_SSE_MOVU_P_RR : InstrItinClass;
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def IIC_SSE_MOVU_P_RM : InstrItinClass;
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def IIC_SSE_MOVU_P_MR : InstrItinClass;
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def IIC_SSE_MOVDQ : InstrItinClass;
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def IIC_SSE_MOVD_ToGP : InstrItinClass;
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def IIC_SSE_MOVQ_RR : InstrItinClass;
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def IIC_SSE_MOV_LH : InstrItinClass;
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def IIC_SSE_LDDQU : InstrItinClass;
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def IIC_SSE_MOVNT : InstrItinClass;
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def IIC_SSE_PHADDSUBD_RR : InstrItinClass;
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def IIC_SSE_PHADDSUBD_RM : InstrItinClass;
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def IIC_SSE_PHADDSUBSW_RR : InstrItinClass;
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def IIC_SSE_PHADDSUBSW_RM : InstrItinClass;
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def IIC_SSE_PHADDSUBW_RR : InstrItinClass;
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def IIC_SSE_PHADDSUBW_RM : InstrItinClass;
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def IIC_SSE_PSHUFB_RR : InstrItinClass;
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def IIC_SSE_PSHUFB_RM : InstrItinClass;
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def IIC_SSE_PSIGN_RR : InstrItinClass;
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def IIC_SSE_PSIGN_RM : InstrItinClass;
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def IIC_SSE_PMADD : InstrItinClass;
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def IIC_SSE_PMULHRSW : InstrItinClass;
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def IIC_SSE_PALIGNRR : InstrItinClass;
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def IIC_SSE_PALIGNRM : InstrItinClass;
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def IIC_SSE_MWAIT : InstrItinClass;
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def IIC_SSE_MONITOR : InstrItinClass;
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def IIC_SSE_PREFETCH : InstrItinClass;
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def IIC_SSE_PAUSE : InstrItinClass;
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def IIC_SSE_LFENCE : InstrItinClass;
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def IIC_SSE_MFENCE : InstrItinClass;
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def IIC_SSE_SFENCE : InstrItinClass;
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def IIC_SSE_LDMXCSR : InstrItinClass;
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def IIC_SSE_STMXCSR : InstrItinClass;
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def IIC_SSE_CVT_PD_RR : InstrItinClass;
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def IIC_SSE_CVT_PD_RM : InstrItinClass;
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def IIC_SSE_CVT_PS_RR : InstrItinClass;
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def IIC_SSE_CVT_PS_RM : InstrItinClass;
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def IIC_SSE_CVT_PI2PS_RR : InstrItinClass;
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def IIC_SSE_CVT_PI2PS_RM : InstrItinClass;
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def IIC_SSE_CVT_Scalar_RR : InstrItinClass;
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def IIC_SSE_CVT_Scalar_RM : InstrItinClass;
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def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass;
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def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass;
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def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass;
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def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
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def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
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def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
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// MMX
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def IIC_MMX_MOV_MM_RM : InstrItinClass;
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def IIC_MMX_MOV_REG_MM : InstrItinClass;
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def IIC_MMX_MOVQ_RM : InstrItinClass;
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def IIC_MMX_MOVQ_RR : InstrItinClass;
|
|
|
|
def IIC_MMX_ALU_RM : InstrItinClass;
|
|
def IIC_MMX_ALU_RR : InstrItinClass;
|
|
def IIC_MMX_ALUQ_RM : InstrItinClass;
|
|
def IIC_MMX_ALUQ_RR : InstrItinClass;
|
|
def IIC_MMX_PHADDSUBW_RM : InstrItinClass;
|
|
def IIC_MMX_PHADDSUBW_RR : InstrItinClass;
|
|
def IIC_MMX_PHADDSUBD_RM : InstrItinClass;
|
|
def IIC_MMX_PHADDSUBD_RR : InstrItinClass;
|
|
def IIC_MMX_PMUL : InstrItinClass;
|
|
def IIC_MMX_MISC_FUNC_MEM : InstrItinClass;
|
|
def IIC_MMX_MISC_FUNC_REG : InstrItinClass;
|
|
def IIC_MMX_PSADBW : InstrItinClass;
|
|
def IIC_MMX_SHIFT_RI : InstrItinClass;
|
|
def IIC_MMX_SHIFT_RM : InstrItinClass;
|
|
def IIC_MMX_SHIFT_RR : InstrItinClass;
|
|
def IIC_MMX_UNPCK_H_RM : InstrItinClass;
|
|
def IIC_MMX_UNPCK_H_RR : InstrItinClass;
|
|
def IIC_MMX_UNPCK_L : InstrItinClass;
|
|
def IIC_MMX_PCK_RM : InstrItinClass;
|
|
def IIC_MMX_PCK_RR : InstrItinClass;
|
|
def IIC_MMX_PSHUF : InstrItinClass;
|
|
def IIC_MMX_PEXTR : InstrItinClass;
|
|
def IIC_MMX_PINSRW : InstrItinClass;
|
|
def IIC_MMX_MASKMOV : InstrItinClass;
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|
|
|
def IIC_MMX_CVT_PD_RR : InstrItinClass;
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|
def IIC_MMX_CVT_PD_RM : InstrItinClass;
|
|
def IIC_MMX_CVT_PS_RR : InstrItinClass;
|
|
def IIC_MMX_CVT_PS_RM : InstrItinClass;
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|
|
|
def IIC_CMPX_LOCK : InstrItinClass;
|
|
def IIC_CMPX_LOCK_8 : InstrItinClass;
|
|
def IIC_CMPX_LOCK_8B : InstrItinClass;
|
|
def IIC_CMPX_LOCK_16B : InstrItinClass;
|
|
|
|
def IIC_XADD_LOCK_MEM : InstrItinClass;
|
|
def IIC_XADD_LOCK_MEM8 : InstrItinClass;
|
|
|
|
def IIC_FILD : InstrItinClass;
|
|
def IIC_FLD : InstrItinClass;
|
|
def IIC_FLD80 : InstrItinClass;
|
|
def IIC_FST : InstrItinClass;
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|
def IIC_FST80 : InstrItinClass;
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|
def IIC_FIST : InstrItinClass;
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|
def IIC_FLDZ : InstrItinClass;
|
|
def IIC_FUCOM : InstrItinClass;
|
|
def IIC_FUCOMI : InstrItinClass;
|
|
def IIC_FCOMI : InstrItinClass;
|
|
def IIC_FNSTSW : InstrItinClass;
|
|
def IIC_FNSTCW : InstrItinClass;
|
|
def IIC_FLDCW : InstrItinClass;
|
|
def IIC_FNINIT : InstrItinClass;
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|
def IIC_FFREE : InstrItinClass;
|
|
def IIC_FNCLEX : InstrItinClass;
|
|
def IIC_WAIT : InstrItinClass;
|
|
def IIC_FXAM : InstrItinClass;
|
|
def IIC_FNOP : InstrItinClass;
|
|
def IIC_FLDL : InstrItinClass;
|
|
def IIC_F2XM1 : InstrItinClass;
|
|
def IIC_FYL2X : InstrItinClass;
|
|
def IIC_FPTAN : InstrItinClass;
|
|
def IIC_FPATAN : InstrItinClass;
|
|
def IIC_FXTRACT : InstrItinClass;
|
|
def IIC_FPREM1 : InstrItinClass;
|
|
def IIC_FPSTP : InstrItinClass;
|
|
def IIC_FPREM : InstrItinClass;
|
|
def IIC_FYL2XP1 : InstrItinClass;
|
|
def IIC_FSINCOS : InstrItinClass;
|
|
def IIC_FRNDINT : InstrItinClass;
|
|
def IIC_FSCALE : InstrItinClass;
|
|
def IIC_FCOMPP : InstrItinClass;
|
|
def IIC_FXSAVE : InstrItinClass;
|
|
def IIC_FXRSTOR : InstrItinClass;
|
|
|
|
def IIC_FXCH : InstrItinClass;
|
|
|
|
// System instructions
|
|
def IIC_CPUID : InstrItinClass;
|
|
def IIC_INT : InstrItinClass;
|
|
def IIC_INT3 : InstrItinClass;
|
|
def IIC_INVD : InstrItinClass;
|
|
def IIC_INVLPG : InstrItinClass;
|
|
def IIC_IRET : InstrItinClass;
|
|
def IIC_HLT : InstrItinClass;
|
|
def IIC_LXS : InstrItinClass;
|
|
def IIC_LTR : InstrItinClass;
|
|
def IIC_RDTSC : InstrItinClass;
|
|
def IIC_RSM : InstrItinClass;
|
|
def IIC_SIDT : InstrItinClass;
|
|
def IIC_SGDT : InstrItinClass;
|
|
def IIC_SLDT : InstrItinClass;
|
|
def IIC_STR : InstrItinClass;
|
|
def IIC_SWAPGS : InstrItinClass;
|
|
def IIC_SYSCALL : InstrItinClass;
|
|
def IIC_SYS_ENTER_EXIT : InstrItinClass;
|
|
def IIC_IN_RR : InstrItinClass;
|
|
def IIC_IN_RI : InstrItinClass;
|
|
def IIC_OUT_RR : InstrItinClass;
|
|
def IIC_OUT_IR : InstrItinClass;
|
|
def IIC_INS : InstrItinClass;
|
|
def IIC_MOV_REG_DR : InstrItinClass;
|
|
def IIC_MOV_DR_REG : InstrItinClass;
|
|
def IIC_MOV_REG_CR : InstrItinClass;
|
|
def IIC_MOV_CR_REG : InstrItinClass;
|
|
def IIC_MOV_REG_SR : InstrItinClass;
|
|
def IIC_MOV_MEM_SR : InstrItinClass;
|
|
def IIC_MOV_SR_REG : InstrItinClass;
|
|
def IIC_MOV_SR_MEM : InstrItinClass;
|
|
def IIC_LAR_RM : InstrItinClass;
|
|
def IIC_LAR_RR : InstrItinClass;
|
|
def IIC_LSL_RM : InstrItinClass;
|
|
def IIC_LSL_RR : InstrItinClass;
|
|
def IIC_LGDT : InstrItinClass;
|
|
def IIC_LIDT : InstrItinClass;
|
|
def IIC_LLDT_REG : InstrItinClass;
|
|
def IIC_LLDT_MEM : InstrItinClass;
|
|
def IIC_PUSH_CS : InstrItinClass;
|
|
def IIC_PUSH_SR : InstrItinClass;
|
|
def IIC_POP_SR : InstrItinClass;
|
|
def IIC_POP_SR_SS : InstrItinClass;
|
|
def IIC_VERR : InstrItinClass;
|
|
def IIC_VERW_REG : InstrItinClass;
|
|
def IIC_VERW_MEM : InstrItinClass;
|
|
def IIC_WRMSR : InstrItinClass;
|
|
def IIC_RDMSR : InstrItinClass;
|
|
def IIC_RDPMC : InstrItinClass;
|
|
def IIC_SMSW : InstrItinClass;
|
|
def IIC_LMSW_REG : InstrItinClass;
|
|
def IIC_LMSW_MEM : InstrItinClass;
|
|
def IIC_ENTER : InstrItinClass;
|
|
def IIC_LEAVE : InstrItinClass;
|
|
def IIC_POP_MEM : InstrItinClass;
|
|
def IIC_POP_REG16 : InstrItinClass;
|
|
def IIC_POP_REG : InstrItinClass;
|
|
def IIC_POP_F : InstrItinClass;
|
|
def IIC_POP_FD : InstrItinClass;
|
|
def IIC_POP_A : InstrItinClass;
|
|
def IIC_PUSH_IMM : InstrItinClass;
|
|
def IIC_PUSH_MEM : InstrItinClass;
|
|
def IIC_PUSH_REG : InstrItinClass;
|
|
def IIC_PUSH_F : InstrItinClass;
|
|
def IIC_PUSH_A : InstrItinClass;
|
|
def IIC_BSWAP : InstrItinClass;
|
|
def IIC_BIT_SCAN_MEM : InstrItinClass;
|
|
def IIC_BIT_SCAN_REG : InstrItinClass;
|
|
def IIC_MOVS : InstrItinClass;
|
|
def IIC_STOS : InstrItinClass;
|
|
def IIC_SCAS : InstrItinClass;
|
|
def IIC_CMPS : InstrItinClass;
|
|
def IIC_MOV : InstrItinClass;
|
|
def IIC_MOV_MEM : InstrItinClass;
|
|
def IIC_AHF : InstrItinClass;
|
|
def IIC_BT_MI : InstrItinClass;
|
|
def IIC_BT_MR : InstrItinClass;
|
|
def IIC_BT_RI : InstrItinClass;
|
|
def IIC_BT_RR : InstrItinClass;
|
|
def IIC_BTX_MI : InstrItinClass;
|
|
def IIC_BTX_MR : InstrItinClass;
|
|
def IIC_BTX_RI : InstrItinClass;
|
|
def IIC_BTX_RR : InstrItinClass;
|
|
def IIC_XCHG_REG : InstrItinClass;
|
|
def IIC_XCHG_MEM : InstrItinClass;
|
|
def IIC_XADD_REG : InstrItinClass;
|
|
def IIC_XADD_MEM : InstrItinClass;
|
|
def IIC_CMPXCHG_MEM : InstrItinClass;
|
|
def IIC_CMPXCHG_REG : InstrItinClass;
|
|
def IIC_CMPXCHG_MEM8 : InstrItinClass;
|
|
def IIC_CMPXCHG_REG8 : InstrItinClass;
|
|
def IIC_CMPXCHG_8B : InstrItinClass;
|
|
def IIC_CMPXCHG_16B : InstrItinClass;
|
|
def IIC_LODS : InstrItinClass;
|
|
def IIC_OUTS : InstrItinClass;
|
|
def IIC_CLC : InstrItinClass;
|
|
def IIC_CLD : InstrItinClass;
|
|
def IIC_CLI : InstrItinClass;
|
|
def IIC_CMC : InstrItinClass;
|
|
def IIC_CLTS : InstrItinClass;
|
|
def IIC_STC : InstrItinClass;
|
|
def IIC_STI : InstrItinClass;
|
|
def IIC_STD : InstrItinClass;
|
|
def IIC_XLAT : InstrItinClass;
|
|
def IIC_AAA : InstrItinClass;
|
|
def IIC_AAD : InstrItinClass;
|
|
def IIC_AAM : InstrItinClass;
|
|
def IIC_AAS : InstrItinClass;
|
|
def IIC_DAA : InstrItinClass;
|
|
def IIC_DAS : InstrItinClass;
|
|
def IIC_BOUND : InstrItinClass;
|
|
def IIC_ARPL_REG : InstrItinClass;
|
|
def IIC_ARPL_MEM : InstrItinClass;
|
|
def IIC_MOVBE : InstrItinClass;
|
|
def IIC_AES : InstrItinClass;
|
|
def IIC_BLEND_MEM : InstrItinClass;
|
|
def IIC_BLEND_NOMEM : InstrItinClass;
|
|
def IIC_CBW : InstrItinClass;
|
|
def IIC_CRC32_REG : InstrItinClass;
|
|
def IIC_CRC32_MEM : InstrItinClass;
|
|
def IIC_SSE_DPPD_RR : InstrItinClass;
|
|
def IIC_SSE_DPPD_RM : InstrItinClass;
|
|
def IIC_SSE_DPPS_RR : InstrItinClass;
|
|
def IIC_SSE_DPPS_RM : InstrItinClass;
|
|
def IIC_MMX_EMMS : InstrItinClass;
|
|
def IIC_SSE_EXTRACTPS_RR : InstrItinClass;
|
|
def IIC_SSE_EXTRACTPS_RM : InstrItinClass;
|
|
def IIC_SSE_INSERTPS_RR : InstrItinClass;
|
|
def IIC_SSE_INSERTPS_RM : InstrItinClass;
|
|
def IIC_SSE_MPSADBW_RR : InstrItinClass;
|
|
def IIC_SSE_MPSADBW_RM : InstrItinClass;
|
|
def IIC_SSE_PMULLD_RR : InstrItinClass;
|
|
def IIC_SSE_PMULLD_RM : InstrItinClass;
|
|
def IIC_SSE_ROUNDPS_REG : InstrItinClass;
|
|
def IIC_SSE_ROUNDPS_MEM : InstrItinClass;
|
|
def IIC_SSE_ROUNDPD_REG : InstrItinClass;
|
|
def IIC_SSE_ROUNDPD_MEM : InstrItinClass;
|
|
def IIC_SSE_POPCNT_RR : InstrItinClass;
|
|
def IIC_SSE_POPCNT_RM : InstrItinClass;
|
|
def IIC_SSE_PCLMULQDQ_RR : InstrItinClass;
|
|
def IIC_SSE_PCLMULQDQ_RM : InstrItinClass;
|
|
|
|
def IIC_NOP : InstrItinClass;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Processor instruction itineraries.
|
|
|
|
// IssueWidth is analogous to the number of decode units. Core and its
|
|
// descendents, including Nehalem and SandyBridge have 4 decoders.
|
|
// Resources beyond the decoder operate on micro-ops and are bufferred
|
|
// so adjacent micro-ops don't directly compete.
|
|
//
|
|
// MicroOpBufferSize > 1 indicates that RAW dependencies can be
|
|
// decoded in the same cycle. The value 32 is a reasonably arbitrary
|
|
// number of in-flight instructions.
|
|
//
|
|
// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
|
|
// indicates high latency opcodes. Alternatively, InstrItinData
|
|
// entries may be included here to define specific operand
|
|
// latencies. Since these latencies are not used for pipeline hazards,
|
|
// they do not need to be exact.
|
|
//
|
|
// The GenericModel contains no instruction itineraries.
|
|
def GenericModel : SchedMachineModel {
|
|
let IssueWidth = 4;
|
|
let MicroOpBufferSize = 32;
|
|
let LoadLatency = 4;
|
|
let HighLatency = 10;
|
|
let PostRAScheduler = 0;
|
|
}
|
|
|
|
include "X86ScheduleAtom.td"
|
|
include "X86SchedSandyBridge.td"
|
|
include "X86SchedHaswell.td"
|
|
include "X86ScheduleSLM.td"
|
|
include "X86ScheduleBtVer2.td"
|
|
|