maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen
History
Digger Lin 41ca91f299 [AIX][XCOFF] Output XCOFF object text section header and symbol entry for program code. 
SUMMARY
Original form of this patch is provided by Stefan Pintillie.

The patch try to output program code section header , symbol entry for program code (PR) and Instruction into the raw text section.
The patch include how to alignment and layout the CSection in the text section.
The patch also reorganize the code , put some codes into a function(XCOFFObjectWriter::writeSymbolTableEntryForControlSection)
Additional: We can not add raw data of text section test in the patch, If want to output raw text section data,it need a function description patch first.

Reviewers: hubert.reinterpretcast, sfertile, jasonliu, xingxue.
Subscribers: wuzish, nemanjai, hiraditya, MaskRay, jsjji.

Differential Revision: https://reviews.llvm.org/D66969

llvm-svn: 374914
 		2019-10-15 17:09:54 +00:00
..
AArch64 [DebugInfo] Remove some users of DBG_VALUEs IsIndirect field 2019-10-15 10:46:24 +00:00
AMDGPU [AMDGPU] Support mov dpp with 64 bit operands 2019-10-15 16:41:15 +00:00
ARC
…
ARM [DebugInfo] Remove some users of DBG_VALUEs IsIndirect field 2019-10-15 10:46:24 +00:00
AVR
…
BPF [BPF] Remove relocation for patchable externs 2019-10-10 15:33:09 +00:00
Generic Reapply r374743 with a fix for the ocaml binding 2019-10-14 16:15:14 +00:00
Hexagon [ModuloSchedule] removeBranch() *before* creating the trip count condition 2019-10-03 17:10:32 +00:00
Inputs
…
Lanai [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
MIR [Alignment] Migrate Attribute::getWith(Stack)Alignment 2019-10-15 12:56:24 +00:00
MSP430 [DAGCombiner] add operation legality checks before creating shift ops (PR43542) 2019-10-03 21:34:04 +00:00
Mips [MIPS GlobalISel] Add MSA registers to fprb. Select vector load, store 2019-10-15 09:30:08 +00:00
NVPTX [NVPTX] Restructure shfl instrinsics and add variants that return a predicate. 2019-10-14 16:53:34 +00:00
PowerPC [AIX][XCOFF] Output XCOFF object text section header and symbol entry for program code. 2019-10-15 17:09:54 +00:00
RISCV [RISCV] Support fast calling convention 2019-10-15 02:04:29 +00:00
SPARC
…
SystemZ [FPEnv] Strict FP tests should use the requisite function attributes. 2019-10-04 17:03:46 +00:00
Thumb (Re)generate various tests. NFC 2019-10-08 16:16:26 +00:00
Thumb2 [ARM] Selection for MVE VMOVN 2019-10-14 15:19:33 +00:00
WebAssembly [WebAssembly] Trapping fptoint builtins and intrinsics 2019-10-15 01:11:51 +00:00
WinCFGuard
…
WinEH [Windows] Replace TrapUnreachable with an int3 insertion pass 2019-09-09 23:04:25 +00:00
X86 [DAGCombiner] fold select-of-constants based on sign-bit test 2019-10-15 15:23:57 +00:00
XCore
…