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llvm-project/llvm/lib/Target/RISCV
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Alex Bradbury 13ce95b77f [RISCV] Bugfix createRISCVELFObjectWriter 
r315275 set the IsLittleEndian parameter incorrectly. This patch corrects 
this, and adds a test to ensure such mistakes will be caught in the future.

llvm-svn: 316091
 		2017-10-18 16:11:31 +00:00
..
AsmParser [Asm] Add debug tracing in table-generated assembly matcher 2017-10-11 09:17:43 +00:00
Disassembler [RISCV] Add support for disassembly 2017-09-17 14:36:28 +00:00
InstPrinter [RISCV] Add support for all RV32I instructions 2017-09-17 14:27:35 +00:00
MCTargetDesc [RISCV] Bugfix createRISCVELFObjectWriter 2017-10-18 16:11:31 +00:00
TargetInfo [RISCV] Add bare-bones RISC-V MCTargetDesc 2016-11-01 23:47:30 +00:00
CMakeLists.txt [RISCV] Add support for disassembly 2017-09-17 14:36:28 +00:00
LLVMBuild.txt [RISCV] Add support for disassembly 2017-09-17 14:36:28 +00:00
RISCV.td [RISCV] Add basic RISCVAsmParser 2017-08-08 14:32:35 +00:00
RISCVInstrFormats.td [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
RISCVInstrInfo.td [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
RISCVRegisterInfo.td
…
RISCVTargetMachine.cpp Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine" 2017-10-12 22:57:28 +00:00
RISCVTargetMachine.h Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine" 2017-10-12 22:57:28 +00:00