forked from OSchip/llvm-project
189 lines
3.1 KiB
LLVM
189 lines
3.1 KiB
LLVM
; FIXME: FastISel currently returns false if it hits code that uses VSX
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; registers and with -fast-isel-abort=1 turned on the test case will then fail.
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; When fastisel better supports VSX fix up this test case.
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;
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
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define zeroext i1 @rettrue() nounwind {
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entry:
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; ELF64-LABEL: rettrue
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; ELF64: li 3, 1
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; ELF64: blr
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ret i1 true
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}
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define zeroext i1 @retfalse() nounwind {
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entry:
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; ELF64-LABEL: retfalse
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; ELF64: li 3, 0
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; ELF64: blr
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ret i1 false
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}
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define signext i1 @retstrue() nounwind {
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entry:
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; ELF64-LABEL: retstrue
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; ELF64: li 3, -1
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; ELF64: blr
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ret i1 true
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}
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define signext i1 @retsfalse() nounwind {
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entry:
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; ELF64-LABEL: retsfalse
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; ELF64: li 3, 0
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; ELF64: blr
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ret i1 false
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}
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define signext i8 @ret2(i8 signext %a) nounwind {
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entry:
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; ELF64-LABEL: ret2
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; ELF64: extsb
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; ELF64: blr
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ret i8 %a
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}
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define zeroext i8 @ret3(i8 signext %a) nounwind {
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entry:
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; ELF64-LABEL: ret3
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
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; ELF64: blr
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ret i8 %a
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}
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define signext i16 @ret4(i16 signext %a) nounwind {
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entry:
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; ELF64-LABEL: ret4
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; ELF64: extsh
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; ELF64: blr
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ret i16 %a
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}
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define zeroext i16 @ret5(i16 signext %a) nounwind {
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entry:
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; ELF64-LABEL: ret5
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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; ELF64: blr
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ret i16 %a
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}
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define i16 @ret6(i16 %a) nounwind {
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entry:
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; ELF64-LABEL: ret6
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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; ELF64: blr
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ret i16 %a
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}
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define signext i32 @ret7(i32 signext %a) nounwind {
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entry:
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; ELF64-LABEL: ret7
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; ELF64: extsw
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; ELF64: blr
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ret i32 %a
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}
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define zeroext i32 @ret8(i32 signext %a) nounwind {
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entry:
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; ELF64-LABEL: ret8
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
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; ELF64: blr
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ret i32 %a
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}
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define i32 @ret9(i32 %a) nounwind {
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entry:
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; ELF64-LABEL: ret9
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
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; ELF64: blr
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ret i32 %a
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}
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define i64 @ret10(i64 %a) nounwind {
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entry:
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; ELF64-LABEL: ret10
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; ELF64-NOT: exts
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; ELF64-NOT: rldicl
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; ELF64: blr
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ret i64 %a
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}
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define float @ret11(float %a) nounwind {
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entry:
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; ELF64-LABEL: ret11
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; ELF64: blr
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ret float %a
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}
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define double @ret12(double %a) nounwind {
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entry:
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; ELF64-LABEL: ret12
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; ELF64: blr
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ret double %a
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}
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define i8 @ret13() nounwind {
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entry:
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; ELF64-LABEL: ret13
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; ELF64: li
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; ELF64: blr
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ret i8 15;
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}
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define i16 @ret14() nounwind {
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entry:
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; ELF64-LABEL: ret14
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; ELF64: li
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; ELF64: blr
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ret i16 -225;
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}
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define i32 @ret15() nounwind {
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entry:
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; ELF64-LABEL: ret15
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; ELF64: lis
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; ELF64: ori
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; ELF64: blr
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ret i32 278135;
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}
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define i64 @ret16() nounwind {
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entry:
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; ELF64-LABEL: ret16
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; ELF64: li
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; ELF64: sldi
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; ELF64: oris
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; ELF64: ori
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; ELF64: blr
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ret i64 27813515225;
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}
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define float @ret17() nounwind {
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entry:
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; ELF64-LABEL: ret17
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; ELF64: addis
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; ELF64: lfs
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; ELF64: blr
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ret float 2.5;
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}
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define double @ret18() nounwind {
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entry:
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; ELF64-LABEL: ret18
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; ELF64: addis
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; ELF64: lfd
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; ELF64: blr
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ret double 2.5e-33;
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}
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define zeroext i32 @ret19() nounwind {
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entry:
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; ELF64-LABEL: ret19
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; ELF64: li
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; ELF64: oris
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; ELF64: ori
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; ELF64: blr
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ret i32 -1
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}
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