forked from OSchip/llvm-project
832 lines
31 KiB
LLVM
832 lines
31 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test vector multiply intrinsic instructions
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;;;
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;;; Note:
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;;; We test VMUL*vvl, VMUL*vvl_v, VMUL*rvl, VMUL*rvl_v, VMUL*ivl, VMUL*ivl_v,
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;;; VMUL*vvml_v, VMUL*rvml_v, and VMUL*ivml_v instructions.
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulul_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vmulul_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.l %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmulul.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmulul.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulul_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vmulul_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.l %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmulul.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmulul.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulul_vsvl(i64 %0, <256 x double> %1) {
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; CHECK-LABEL: vmulul_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vmulu.l %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmulul.vsvl(i64 %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmulul.vsvl(i64, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulul_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vmulul_vsvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vmulu.l %v1, %s0, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmulul.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmulul.vsvvl(i64, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulul_vsvl_imm(<256 x double> %0) {
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; CHECK-LABEL: vmulul_vsvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.l %v0, 8, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vmulul.vsvl(i64 8, <256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulul_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vmulul_vsvvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.l %v1, 8, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmulul.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulul_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vmulul_vvvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.l %v2, %v0, %v1, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vmulul.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmulul.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulul_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vmulul_vsvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vmulu.l %v1, %s0, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vmulul.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmulul.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulul_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
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; CHECK-LABEL: vmulul_vsvmvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.l %v1, 8, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmulul.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmuluw_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vmuluw_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.w %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmuluw.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmuluw.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmuluw_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vmuluw_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.w %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmuluw.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmuluw.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmuluw_vsvl(i32 signext %0, <256 x double> %1) {
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; CHECK-LABEL: vmuluw_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vmulu.w %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmuluw.vsvl(i32 %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmuluw.vsvl(i32, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmuluw_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vmuluw_vsvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vmulu.w %v1, %s0, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmuluw.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmuluw.vsvvl(i32, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmuluw_vsvl_imm(<256 x double> %0) {
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; CHECK-LABEL: vmuluw_vsvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.w %v0, 8, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vmuluw.vsvl(i32 8, <256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmuluw_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vmuluw_vsvvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.w %v1, 8, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmuluw.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmuluw_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vmuluw_vvvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.w %v2, %v0, %v1, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vmuluw.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmuluw.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmuluw_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vmuluw_vsvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vmulu.w %v1, %s0, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vmuluw.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmuluw.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmuluw_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
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; CHECK-LABEL: vmuluw_vsvmvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmulu.w %v1, 8, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmuluw.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulswsx_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vmulswsx_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmuls.w.sx %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmulswsx.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmulswsx.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulswsx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vmulswsx_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmuls.w.sx %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmulswsx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmulswsx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulswsx_vsvl(i32 signext %0, <256 x double> %1) {
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; CHECK-LABEL: vmulswsx_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vmuls.w.sx %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmulswsx.vsvl(i32 %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmulswsx.vsvl(i32, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulswsx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vmulswsx_vsvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vmuls.w.sx %v1, %s0, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vmulswsx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulswsx.vsvvl(i32, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswsx_vsvl_imm(<256 x double> %0) {
|
|
; CHECK-LABEL: vmulswsx_vsvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.w.sx %v0, 8, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%2 = tail call fast <256 x double> @llvm.ve.vl.vmulswsx.vsvl(i32 8, <256 x double> %0, i32 256)
|
|
ret <256 x double> %2
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswsx_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vmulswsx_vsvvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.w.sx %v1, 8, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vmulswsx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswsx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: vmulswsx_vvvmvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.w.sx %v2, %v0, %v1, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.vmulswsx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulswsx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswsx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: vmulswsx_vsvmvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vmuls.w.sx %v1, %s0, %v0, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.vmulswsx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulswsx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswsx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vmulswsx_vsvmvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.w.sx %v1, 8, %v0, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vmulswsx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswzx_vvvl(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vmulswzx_vvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.w.zx %v0, %v0, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vmulswzx.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulswzx.vvvl(<256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswzx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vmulswzx_vvvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.w.zx %v2, %v0, %v1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vmulswzx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulswzx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswzx_vsvl(i32 signext %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vmulswzx_vsvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 256
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vmuls.w.zx %v0, %s0, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vmulswzx.vsvl(i32 %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulswzx.vsvl(i32, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswzx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vmulswzx_vsvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vmuls.w.zx %v1, %s0, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vmulswzx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulswzx.vsvvl(i32, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswzx_vsvl_imm(<256 x double> %0) {
|
|
; CHECK-LABEL: vmulswzx_vsvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.w.zx %v0, 8, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%2 = tail call fast <256 x double> @llvm.ve.vl.vmulswzx.vsvl(i32 8, <256 x double> %0, i32 256)
|
|
ret <256 x double> %2
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswzx_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vmulswzx_vsvvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.w.zx %v1, 8, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vmulswzx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswzx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: vmulswzx_vvvmvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.w.zx %v2, %v0, %v1, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.vmulswzx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulswzx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswzx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: vmulswzx_vsvmvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vmuls.w.zx %v1, %s0, %v0, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.vmulswzx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulswzx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulswzx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vmulswzx_vsvmvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.w.zx %v1, 8, %v0, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vmulswzx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulsl_vvvl(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vmulsl_vvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.l %v0, %v0, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vmulsl.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulsl.vvvl(<256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulsl_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vmulsl_vvvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.l %v2, %v0, %v1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vmulsl.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulsl.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulsl_vsvl(i64 %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vmulsl_vsvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s1, 256
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vmuls.l %v0, %s0, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vmulsl.vsvl(i64 %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulsl.vsvl(i64, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulsl_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vmulsl_vsvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vmuls.l %v1, %s0, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vmulsl.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulsl.vsvvl(i64, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulsl_vsvl_imm(<256 x double> %0) {
|
|
; CHECK-LABEL: vmulsl_vsvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.l %v0, 8, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%2 = tail call fast <256 x double> @llvm.ve.vl.vmulsl.vsvl(i64 8, <256 x double> %0, i32 256)
|
|
ret <256 x double> %2
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulsl_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vmulsl_vsvvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.l %v1, 8, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vmulsl.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulsl_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: vmulsl_vvvmvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.l %v2, %v0, %v1, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vmulsl.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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|
|
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmulsl.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
|
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define fastcc <256 x double> @vmulsl_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
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; CHECK-LABEL: vmulsl_vsvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vmuls.l %v1, %s0, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
|
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vmulsl.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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|
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; Function Attrs: nounwind readnone
|
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declare <256 x double> @llvm.ve.vl.vmulsl.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulsl_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
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; CHECK-LABEL: vmulsl_vsvmvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
|
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmuls.l %v1, 8, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
|
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmulsl.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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|
|
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vmulslw_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vmulslw_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
|
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vmuls.l.w %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmulslw.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
|
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}
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|
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; Function Attrs: nounwind readnone
|
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declare <256 x double> @llvm.ve.vl.vmulslw.vvvl(<256 x double>, <256 x double>, i32)
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|
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; Function Attrs: nounwind readnone
|
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define fastcc <256 x double> @vmulslw_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
|
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; CHECK-LABEL: vmulslw_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
|
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; CHECK-NEXT: lvl %s0
|
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; CHECK-NEXT: vmuls.l.w %v2, %v0, %v1
|
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; CHECK-NEXT: lea %s16, 256
|
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; CHECK-NEXT: lvl %s16
|
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; CHECK-NEXT: vor %v0, (0)1, %v2
|
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; CHECK-NEXT: b.l.t (, %s10)
|
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmulslw.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
|
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ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulslw.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulslw_vsvl(i32 signext %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vmulslw_vsvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 256
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vmuls.l.w %v0, %s0, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vmulslw.vsvl(i32 %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulslw.vsvl(i32, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulslw_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vmulslw_vsvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vmuls.l.w %v1, %s0, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vmulslw.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vmulslw.vsvvl(i32, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulslw_vsvl_imm(<256 x double> %0) {
|
|
; CHECK-LABEL: vmulslw_vsvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.l.w %v0, 8, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%2 = tail call fast <256 x double> @llvm.ve.vl.vmulslw.vsvl(i32 8, <256 x double> %0, i32 256)
|
|
ret <256 x double> %2
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vmulslw_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vmulslw_vsvvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vmuls.l.w %v1, 8, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vmulslw.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128)
|
|
ret <256 x double> %3
|
|
}
|