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llvm-project/llvm/test/CodeGen
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Jiangning Liu f841b3b79e Optimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG Builder and type 
legalization stage. With those two optimizations, fewer signed/zero extension
instructions can be inserted, and then we can expose more opportunities to
Machine CSE pass in back-end.

llvm-svn: 216066
 		2014-08-20 12:05:15 +00:00
..
AArch64 Optimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG Builder and type 2014-08-20 12:05:15 +00:00
ARM ARM: Fix codegen for rbit intrinsic 2014-08-20 10:40:20 +00:00
CPP IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
Generic Use "weak alias" instead of "alias weak" 2014-07-30 22:51:54 +00:00
Hexagon DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range. 2014-08-06 00:21:25 +00:00
Inputs
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MSP430 Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
Mips Fix fmul combines with constant splat vectors 2014-08-16 10:14:19 +00:00
NVPTX [NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types 2014-07-23 20:23:49 +00:00
PowerPC Reapply [FastISel] Let the target decide first if it wants to materialize a constant (215588). 2014-08-19 19:05:24 +00:00
R600 R600/SI: Move all fabs / fneg handling to patterns 2014-08-15 18:42:22 +00:00
SPARC IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
SystemZ IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
Thumb ARM: Fix and re-enable load/store optimizer for Thumb1. 2014-08-15 17:00:30 +00:00
Thumb2 ARM: do not generate BLX instructions on Cortex-M CPUs. 2014-08-06 11:13:14 +00:00
X86 [x32] Fix FrameIndex check in SelectLEA64_32Addr 2014-08-20 11:59:22 +00:00
XCore llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32. 2014-07-04 11:58:03 +00:00