llvm-project/llvm/test/MC/Disassembler/Mips/mips64r5
Daniel Sanders f8bb23e509 [mips] Range check uimm16 and fix several bugs this revealed.
Summary:
The bugs were:
* teq and similar take 4-bit unsigned immediates on microMIPS.
* teqi and similar have side-effects like teq do.
* shll_s.w and shra_r.w take 5-bit unsigned immediates.
* The various DSP ext* instructions take a 5-bit immediate.
* repl.qh takes an 8-bit unsigned immediate.
* repl.ph takes a 10-bit unsigned immediate.
* rddsp/wrdsp take a 10-bit unsigned immediate.
* teqi and similar take signed 16-bit immediates (10-bit for microMIPS).
* Out-of-range immediate macros for or/xor take a simm32/simm64 depending
  on architecture. I'll fix the simm64 case properly when I reach simm32.

lui is a bit more lenient than GAS and accepts signed immediates in addition
to unsigned. This is because MipsMCExpr can produce signed values when
constant folding and it currently lacks a way of knowing it should fold to
an unsigned value.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15446

llvm-svn: 259360
2016-02-01 15:13:31 +00:00
..
invalid-xfail.txt [mips] Add missing disassembler tests for MIPS64-MIPS64R5. 2015-09-11 16:24:11 +00:00
valid-mips64r5-el.txt [mips] Remap move as or. 2015-08-11 08:56:25 +00:00
valid-mips64r5.txt [mips] Range check uimm16 and fix several bugs this revealed. 2016-02-01 15:13:31 +00:00
valid-xfail-mips64r5.txt
valid-xfail.txt [mips] Add missing disassembler tests for MIPS64-MIPS64R5. 2015-09-11 16:24:11 +00:00