forked from OSchip/llvm-project
f8bb23e509
Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360 |
||
|---|---|---|
| .. | ||
| dsp | ||
| dspr2 | ||
| eva | ||
| micromips-dsp | ||
| micromips-dspr2 | ||
| micromips32r3 | ||
| micromips32r6 | ||
| micromips64r6 | ||
| mips1 | ||
| mips2 | ||
| mips3 | ||
| mips4 | ||
| mips32 | ||
| mips32r2 | ||
| mips32r3 | ||
| mips32r5 | ||
| mips32r6 | ||
| mips64 | ||
| mips64r2 | ||
| mips64r3 | ||
| mips64r5 | ||
| mips64r6 | ||
| msa | ||
| lit.local.cfg | ||