forked from OSchip/llvm-project
212 lines
7.9 KiB
ArmAsm
212 lines
7.9 KiB
ArmAsm
// REQUIRES: arm
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// RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabihf --arm-add-build-attributes %s -o %t.o
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// RUN: ld.lld --fix-cortex-a8 -verbose %t.o -o %t2 2>&1 | FileCheck %s
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// RUN: llvm-objdump -d %t2 --start-address=0x1a004 --stop-address=0x1a024 --no-show-raw-insn | FileCheck --check-prefix=CHECK-PATCHES %s
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// RUN: llvm-objdump -d %t2 --start-address=0x12ffa --stop-address=0x13002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE1 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x13ffa --stop-address=0x14002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE2 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x14ffa --stop-address=0x15002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE3 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x15ff4 --stop-address=0x16002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE4 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x16ffa --stop-address=0x17002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE5 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x17ffa --stop-address=0x18002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE6 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x18ffa --stop-address=0x19002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE7 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x19ff4 --stop-address=0x1a002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE8 %s
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// RUN: ld.lld --fix-cortex-a8 -verbose -r %t.o -o %t3 2>&1 | FileCheck --check-prefix=CHECK-RELOCATABLE-LLD %s
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// RUN: llvm-objdump --no-show-raw-insn -d %t3 --start-address=0xffa --stop-address=0x1002 | FileCheck --check-prefix=CHECK-RELOCATABLE %s
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// CHECK: ld.lld: detected cortex-a8-657419 erratum sequence starting at 12FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 13FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 14FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 15FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 16FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 17FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 18FFE in unpatched output.
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/// We do not detect errors when doing a relocatable link as we don't know what
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/// the final addresses are.
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// CHECK-RELOCATABLE-LLD-NOT: ld.lld: detected cortex-a8-657419 erratum sequence
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/// Basic tests for the -fix-cortex-a8 erratum fix. The full details of the
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/// erratum and the patch are in ARMA8ErrataFix.cpp . The test creates an
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/// instance of the erratum every 4KiB (32-bit non-branch, followed by 32-bit
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/// branch instruction, where the branch instruction spans two 4 KiB regions,
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/// and the branch destination is in the first 4KiB region.
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///
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/// Test each 32-bit branch b.w, bcc.w, bl, blx. For b.w, bcc.w, and bl we
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/// check the relocated and non-relocated forms. The blx instruction
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/// always has a relocation in assembler.
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.syntax unified
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.thumb
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.text
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.global _start
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.type _start, %function
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.balign 4096
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.thumb_func
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_start:
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nop.w
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.space 4086
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.thumb_func
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.global target
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.type target, %function
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target:
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/// 32-bit Branch spans 2 4KiB regions, preceded by a 32-bit non branch
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/// instruction, expect a patch.
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nop.w
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b.w target
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// CALLSITE1: 00012ffa target:
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// CALLSITE1-NEXT: 12ffa: nop.w
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// CALLSITE1-NEXT: 12ffe: b.w #28674
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/// Expect no patch when doing a relocatable link ld -r.
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// CHECK-RELOCATABLE: 00000ffa target:
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// CHECK-RELOCATABLE-NEXT: ffa: nop.w
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// CHECK-RELOCATABLE-NEXT: ffe: b.w #-4
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.space 4088
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.type target2, %function
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.local target2
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target2:
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/// 32-bit Branch and link spans 2 4KiB regions, preceded by a 32-bit
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/// non branch instruction, expect a patch.
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nop.w
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bl target2
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// CALLSITE2: 00013ffa target2:
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// CALLSITE2-NEXT: 13ffa: nop.w
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// CALLSITE2-NEXT: 13ffe: bl #24582
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.space 4088
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.type target3, %function
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.local target3
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target3:
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/// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
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/// non branch instruction, expect a patch.
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nop.w
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beq.w target3
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// CALLSITE3: 00014ffa target3:
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// CALLSITE3-NEXT: 14ffa: nop.w
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// CALLSITE3-NEXT: 14ffe: beq.w #20490
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.space 4082
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.type target4, %function
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.local target4
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.arm
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target4:
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bx lr
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.space 2
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.thumb
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/// 32-bit Branch link and exchange spans 2 4KiB regions, preceded by a
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/// 32-bit non branch instruction, blx always goes via relocation. Expect
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/// a patch.
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nop.w
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blx target4
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/// Target = 0x19010 __CortexA8657417_15FFE
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// CALLSITE4: 00015ff4 target4:
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// CALLSITE4-NEXT: 15ff4: bx lr
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// CALLSITE4: 15ff8: 00 00 .short 0x0000
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// CALLSITE4: 15ffa: nop.w
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// CALLSITE4-NEXT: 15ffe: blx #16400
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/// Separate sections for source and destination of branches to force
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/// a relocation.
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.section .text.0, "ax", %progbits
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.balign 2
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.global target5
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.type target5, %function
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target5:
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nop.w
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.section .text.1, "ax", %progbits
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.space 4084
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/// 32-bit branch spans 2 4KiB regions, preceded by a 32-bit non branch
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/// instruction, expect a patch. Branch to global symbol so goes via a
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/// relocation.
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nop.w
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b.w target5
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/// Target = 0x19014 __CortexA8657417_16FFE
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// CALLSITE5: 16ffa: nop.w
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// CALLSITE5-NEXT: 16ffe: b.w #12306
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.section .text.2, "ax", %progbits
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.balign 2
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.global target6
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.type target6, %function
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target6:
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nop.w
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.section .text.3, "ax", %progbits
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.space 4084
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/// 32-bit branch and link spans 2 4KiB regions, preceded by a 32-bit
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/// non branch instruction, expect a patch. Branch to global symbol so
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/// goes via a relocation.
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nop.w
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bl target6
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/// Target = 0x19018 __CortexA8657417_17FFE
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// CALLSITE6: 17ffa: nop.w
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// CALLSITE6-NEXT: 17ffe: bl #8214
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.section .text.4, "ax", %progbits
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.global target7
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.type target7, %function
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target7:
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nop.w
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.section .text.5, "ax", %progbits
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.space 4084
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/// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
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/// non branch instruction, expect a patch. Branch to global symbol so
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/// goes via a relocation.
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nop.w
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bne.w target7
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// CALLSITE7: 18ffa: nop.w
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// CALLSITE7-NEXT: 18ffe: bne.w #4122
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.section .text.6, "ax", %progbits
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.space 4082
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.arm
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.global target8
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.type target8, %function
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target8:
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bx lr
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.section .text.7, "ax", %progbits
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.space 2
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.thumb
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/// 32-bit Branch link spans 2 4KiB regions, preceded by a 32-bit non branch
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/// instruction, expect a patch. The target of the BL is in ARM state so we
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/// expect it to be turned into a BLX. The patch must be in ARM state to
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/// avoid a state change thunk.
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nop.w
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bl target8
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// CALLSITE8: 00019ff4 target8:
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// CALLSITE8-NEXT: 19ff4: bx lr
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// CALLSITE8: 19ff8: 00 00 .short 0x0000
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// CALLSITE8: 19ffa: nop.w
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// CALLSITE8-NEXT: 19ffe: blx #32
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// CHECK-PATCHES: 0001a004 __CortexA8657417_12FFE:
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// CHECK-PATCHES-NEXT: 1a004: b.w #-28686
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// CHECK-PATCHES: 0001a008 __CortexA8657417_13FFE:
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// CHECK-PATCHES-NEXT: 1a008: b.w #-24594
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// CHECK-PATCHES: 0001a00c __CortexA8657417_14FFE:
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// CHECK-PATCHES-NEXT: 1a00c: b.w #-20502
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// CHECK-PATCHES: 0001a010 __CortexA8657417_15FFE:
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// CHECK-PATCHES-NEXT: 1a010: b #-16420
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// CHECK-PATCHES: 0001a014 __CortexA8657417_16FFE:
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// CHECK-PATCHES-NEXT: 1a014: b.w #-16406
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// CHECK-PATCHES: 0001a018 __CortexA8657417_17FFE:
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// CHECK-PATCHES-NEXT: 1a018: b.w #-12314
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// CHECK-PATCHES: 0001a01c __CortexA8657417_18FFE:
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// CHECK-PATCHES-NEXT: 1a01c: b.w #-8222
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// CHECK-PATCHES: 0001a020 __CortexA8657417_19FFE:
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// CHECK-PATCHES-NEXT: 1a020: b #-52
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