forked from OSchip/llvm-project
211 lines
9.4 KiB
LLVM
211 lines
9.4 KiB
LLVM
; RUN: opt -S -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; Test predication of non-void instructions, specifically (i) that these
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; instructions permit vectorization and (ii) the creation of an insertelement
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; and a Phi node. We check the full 2-element sequence for the first
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; instruction; For the rest we'll just make sure they get predicated based
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; on the code generated for the first element.
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define void @test(i32* nocapture %asd, i32* nocapture %aud,
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i32* nocapture %asr, i32* nocapture %aur) {
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entry:
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br label %for.body
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for.cond.cleanup: ; preds = %if.end
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ret void
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; CHECK-LABEL: test
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; CHECK: vector.body:
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; CHECK: %[[SDEE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0
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; CHECK: %[[SDCC:[a-zA-Z0-9]+]] = icmp eq i1 %[[SDEE]], true
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; CHECK: br i1 %[[SDCC]], label %[[CSD:[a-zA-Z0-9.]+]], label %[[ESD:[a-zA-Z0-9.]+]]
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; CHECK: [[CSD]]:
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; CHECK: %[[SDA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
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; CHECK: %[[SDA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
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; CHECK: %[[SD0:[a-zA-Z0-9]+]] = sdiv i32 %[[SDA0]], %[[SDA1]]
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; CHECK: %[[SD1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[SD0]], i32 0
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; CHECK: br label %[[ESD]]
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; CHECK: [[ESD]]:
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; CHECK: %[[SDR:[a-zA-Z0-9]+]] = phi <2 x i32> [ undef, %vector.body ], [ %[[SD1]], %[[CSD]] ]
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; CHECK: %[[SDEEH:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 1
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; CHECK: %[[SDCCH:[a-zA-Z0-9]+]] = icmp eq i1 %[[SDEEH]], true
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; CHECK: br i1 %[[SDCCH]], label %[[CSDH:[a-zA-Z0-9.]+]], label %[[ESDH:[a-zA-Z0-9.]+]]
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; CHECK: [[CSDH]]:
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; CHECK: %[[SDA0H:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 1
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; CHECK: %[[SDA1H:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 1
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; CHECK: %[[SD0H:[a-zA-Z0-9]+]] = sdiv i32 %[[SDA0H]], %[[SDA1H]]
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; CHECK: %[[SD1H:[a-zA-Z0-9]+]] = insertelement <2 x i32> %[[SDR]], i32 %[[SD0H]], i32 1
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; CHECK: br label %[[ESDH]]
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; CHECK: [[ESDH]]:
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; CHECK: %{{.*}} = phi <2 x i32> [ %[[SDR]], %[[ESD]] ], [ %[[SD1H]], %[[CSDH]] ]
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; CHECK: %[[UDEE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0
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; CHECK: %[[UDCC:[a-zA-Z0-9]+]] = icmp eq i1 %[[UDEE]], true
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; CHECK: br i1 %[[UDCC]], label %[[CUD:[a-zA-Z0-9.]+]], label %[[EUD:[a-zA-Z0-9.]+]]
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; CHECK: [[CUD]]:
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; CHECK: %[[UDA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
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; CHECK: %[[UDA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
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; CHECK: %[[UD0:[a-zA-Z0-9]+]] = udiv i32 %[[UDA0]], %[[UDA1]]
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; CHECK: %[[UD1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[UD0]], i32 0
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; CHECK: br label %[[EUD]]
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; CHECK: [[EUD]]:
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; CHECK: %{{.*}} = phi <2 x i32> [ undef, %{{.*}} ], [ %[[UD1]], %[[CUD]] ]
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; CHECK: %[[SREE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0
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; CHECK: %[[SRCC:[a-zA-Z0-9]+]] = icmp eq i1 %[[SREE]], true
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; CHECK: br i1 %[[SRCC]], label %[[CSR:[a-zA-Z0-9.]+]], label %[[ESR:[a-zA-Z0-9.]+]]
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; CHECK: [[CSR]]:
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; CHECK: %[[SRA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
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; CHECK: %[[SRA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
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; CHECK: %[[SR0:[a-zA-Z0-9]+]] = srem i32 %[[SRA0]], %[[SRA1]]
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; CHECK: %[[SR1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[SR0]], i32 0
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; CHECK: br label %[[ESR]]
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; CHECK: [[ESR]]:
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; CHECK: %{{.*}} = phi <2 x i32> [ undef, %{{.*}} ], [ %[[SR1]], %[[CSR]] ]
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; CHECK: %[[UREE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0
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; CHECK: %[[URCC:[a-zA-Z0-9]+]] = icmp eq i1 %[[UREE]], true
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; CHECK: br i1 %[[URCC]], label %[[CUR:[a-zA-Z0-9.]+]], label %[[EUR:[a-zA-Z0-9.]+]]
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; CHECK: [[CUR]]:
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; CHECK: %[[URA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
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; CHECK: %[[URA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
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; CHECK: %[[UR0:[a-zA-Z0-9]+]] = urem i32 %[[URA0]], %[[URA1]]
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; CHECK: %[[UR1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[UR0]], i32 0
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; CHECK: br label %[[EUR]]
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; CHECK: [[EUR]]:
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; CHECK: %{{.*}} = phi <2 x i32> [ undef, %{{.*}} ], [ %[[UR1]], %[[CUR]] ]
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for.body: ; preds = %if.end, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ]
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%isd = getelementptr inbounds i32, i32* %asd, i64 %indvars.iv
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%iud = getelementptr inbounds i32, i32* %aud, i64 %indvars.iv
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%isr = getelementptr inbounds i32, i32* %asr, i64 %indvars.iv
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%iur = getelementptr inbounds i32, i32* %aur, i64 %indvars.iv
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%lsd = load i32, i32* %isd, align 4
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%lud = load i32, i32* %iud, align 4
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%lsr = load i32, i32* %isr, align 4
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%lur = load i32, i32* %iur, align 4
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%psd = add nsw i32 %lsd, 23
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%pud = add nsw i32 %lud, 24
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%psr = add nsw i32 %lsr, 25
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%pur = add nsw i32 %lur, 26
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%cmp1 = icmp slt i32 %lsd, 100
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %for.body
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%rsd = sdiv i32 %psd, %lsd
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%rud = udiv i32 %pud, %lud
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%rsr = srem i32 %psr, %lsr
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%rur = urem i32 %pur, %lur
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br label %if.end
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if.end: ; preds = %if.then, %for.body
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%ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ]
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%yud.0 = phi i32 [ %rud, %if.then ], [ %pud, %for.body ]
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%ysr.0 = phi i32 [ %rsr, %if.then ], [ %psr, %for.body ]
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%yur.0 = phi i32 [ %rur, %if.then ], [ %pur, %for.body ]
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store i32 %ysd.0, i32* %isd, align 4
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store i32 %yud.0, i32* %iud, align 4
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store i32 %ysr.0, i32* %isr, align 4
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store i32 %yur.0, i32* %iur, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 128
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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define void @test_scalar2scalar(i32* nocapture %asd, i32* nocapture %bsd) {
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entry:
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br label %for.body
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for.cond.cleanup: ; preds = %if.end
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ret void
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; CHECK-LABEL: test_scalar2scalar
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; CHECK: vector.body:
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; CHECK: br i1 %{{.*}}, label %[[THEN:[a-zA-Z0-9.]+]], label %[[FI:[a-zA-Z0-9.]+]]
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; CHECK: [[THEN]]:
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; CHECK: %[[PD:[a-zA-Z0-9]+]] = sdiv i32 %{{.*}}, %{{.*}}
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; CHECK: br label %[[FI]]
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; CHECK: [[FI]]:
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; CHECK: %{{.*}} = phi i32 [ undef, %vector.body ], [ %[[PD]], %[[THEN]] ]
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for.body: ; preds = %if.end, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ]
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%isd = getelementptr inbounds i32, i32* %asd, i64 %indvars.iv
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%lsd = load i32, i32* %isd, align 4
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%isd.b = getelementptr inbounds i32, i32* %bsd, i64 %indvars.iv
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%lsd.b = load i32, i32* %isd.b, align 4
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%psd = add nsw i32 %lsd, 23
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%cmp1 = icmp slt i32 %lsd, 100
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %for.body
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%sd1 = sdiv i32 %psd, %lsd
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%rsd = sdiv i32 %lsd.b, %sd1
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br label %if.end
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if.end: ; preds = %if.then, %for.body
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%ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ]
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store i32 %ysd.0, i32* %isd, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 128
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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define void @pr30172(i32* nocapture %asd, i32* nocapture %bsd) {
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entry:
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br label %for.body
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for.cond.cleanup: ; preds = %if.end
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ret void
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; CHECK-LABEL: pr30172
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; CHECK: vector.body:
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; CHECK: %[[CMP1:.+]] = icmp slt <2 x i32> %[[VAL:.+]], <i32 100, i32 100>
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; CHECK: %[[CMP2:.+]] = icmp sge <2 x i32> %[[VAL]], <i32 200, i32 200>
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; CHECK: %[[XOR:.+]] = xor <2 x i1> %[[CMP1]], <i1 true, i1 true>
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; CHECK: %[[AND1:.+]] = and <2 x i1> %[[XOR]], <i1 true, i1 true>
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; CHECK: %[[OR1:.+]] = or <2 x i1> zeroinitializer, %[[AND1]]
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; CHECK: %[[AND2:.+]] = and <2 x i1> %[[CMP2]], %[[OR1]]
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; CHECK: %[[OR2:.+]] = or <2 x i1> zeroinitializer, %[[AND2]]
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; CHECK: %[[AND3:.+]] = and <2 x i1> %[[CMP1]], <i1 true, i1 true>
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; CHECK: %[[OR3:.+]] = or <2 x i1> %[[OR2]], %[[AND3]]
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; CHECK: %[[EXTRACT:.+]] = extractelement <2 x i1> %[[OR3]], i32 0
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; CHECK: %[[MASK:.+]] = icmp eq i1 %[[EXTRACT]], true
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; CHECK: br i1 %[[MASK]], label %[[THEN:[a-zA-Z0-9.]+]], label %[[FI:[a-zA-Z0-9.]+]]
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; CHECK: [[THEN]]:
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; CHECK: %[[PD:[a-zA-Z0-9]+]] = sdiv i32 %{{.*}}, %{{.*}}
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; CHECK: br label %[[FI]]
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; CHECK: [[FI]]:
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; CHECK: %{{.*}} = phi i32 [ undef, %vector.body ], [ %[[PD]], %[[THEN]] ]
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for.body: ; preds = %if.end, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ]
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%isd = getelementptr inbounds i32, i32* %asd, i64 %indvars.iv
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%lsd = load i32, i32* %isd, align 4
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%isd.b = getelementptr inbounds i32, i32* %bsd, i64 %indvars.iv
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%lsd.b = load i32, i32* %isd.b, align 4
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%psd = add nsw i32 %lsd, 23
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%cmp1 = icmp slt i32 %lsd, 100
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br i1 %cmp1, label %if.then, label %check
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check: ; preds = %for.body
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%cmp2 = icmp sge i32 %lsd, 200
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br i1 %cmp2, label %if.then, label %if.end
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if.then: ; preds = %check, %for.body
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%sd1 = sdiv i32 %psd, %lsd
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%rsd = sdiv i32 %lsd.b, %sd1
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br label %if.end
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if.end: ; preds = %if.then, %check
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%ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %check ]
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store i32 %ysd.0, i32* %isd, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 128
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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