llvm-project/llvm/test/CodeGen
Baptiste Saleil caf1294d95 [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
the compilation time and there is no case for which we see any improvement in
performance. This patch removes this pass and its associated test cases from
the tree.

Differential Revision: https://reviews.llvm.org/D101313

Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-26 17:21:49 -04:00
..
AArch64 AArch64: support atomics in GISel 2021-04-26 14:38:06 +01:00
AMDGPU [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
ARC
ARM [ARM] Expand VMOVRRD simplification pattern 2021-04-26 12:27:38 +01:00
AVR
BPF BPF: remove default .extern data section 2021-04-13 11:35:52 -07:00
Generic Delete le32/le64 targets 2021-04-21 18:44:12 -07:00
Hexagon [Hexagon] Improve lowering of returns of i1 2021-04-22 16:47:52 -05:00
Inputs
Lanai
M68k [DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling 2021-03-19 16:02:31 +00:00
MIR [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
MSP430
Mips [MIPS, test] Fix use of undef FileCheck var 2021-04-02 00:59:49 +01:00
NVPTX [NVPTX] Handle bitcast and ASC(101) when trying to avoid argument copy. 2021-04-06 13:06:00 -07:00
PowerPC [PowerPC] Add vec_ctsl and vec_ctul to altivec.h 2021-04-23 11:03:38 -05:00
RISCV [RISCV] Match splatted load to scalar load + splat. Form strided load during isel. 2021-04-26 13:32:03 -07:00
SPARC
SystemZ
Thumb Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
Thumb2 [ARM] Expand VMOVRRD simplification pattern 2021-04-26 12:27:38 +01:00
VE
WebAssembly [WebAssembly] Fix fixEndsAtEndOfFunction for delegate 2021-04-22 15:32:00 -07:00
WinCFGuard
WinEH
X86 [NFC][X86][AVX2] Add baseline CodeGen/CostModel tests for interleaved loads/stores of i16 w/ strides 2/3/4 2021-04-26 01:13:07 +03:00
XCore